公开(公告)号：US20250105870A1

公开(公告)日：2025-03-27

申请号：US18516182

申请日：2023-11-21

Applicant: Apple Inc.

Inventor： Yu Chang ,  Mitesh D. Katakwar ,  Huabo Chen ,  Huy M. Nguyen

IPC: H04B1/525 ,  H04L25/03

Abstract: Circuits for reflection cancellation in single-ended signaling are disclosed. A transmission circuit includes a control circuit configured to receive a plurality of input signals that include a plurality of symbols having at least one bit and a data driver circuit configured to generate a particular signal on a transmission medium using a particular symbol of the plurality of symbols. The transmission circuit further includes a reflection cancellation circuit configured to, after a generation of the particular signal, generate a reflection cancellation signal on the transmission medium using an inverted value of a different symbol of the plurality of symbols received prior to the particular symbol. A first composite of the particular signal and the cancellation signal is readable at a load as a value of the particular symbol, wherein the load is configured to receive a transmitted signal via the transmission medium.

公开(公告)号：US11811567B1

公开(公告)日：2023-11-07

申请号：US17931090

申请日：2022-09-09

Applicant: Apple Inc.

Inventor： Battaje Vimalesh Rao ,  Jacob S. Schneider ,  Mitesh D. Katakwar

IPC: H04L25/03

CPC classification number: H04L25/03038 ,  H04L25/03057

Abstract: A serial data receiver is disclosed. In one embodiment, a receiver includes an amplifier circuit configured to receive one or more signals that encode a serial data stream that includes a plurality of data symbols and to perform a comparison of the one or more signals to a threshold value to generate a recovered data symbol. The receiver circuit further includes a threshold circuit configured to generate a delayed version of the one or more signals. The threshold circuit is further configured to generate a delayed data symbol using the delayed version of the one or more signals and adjust the threshold value using the delayed data symbol.

公开(公告)号：US10651979B1

公开(公告)日：2020-05-12

申请号：US16431482

申请日：2019-06-04

Applicant: Apple Inc.

Inventor： Mitesh D. Katakwar ,  Seong Hoon Lee ,  Huy M. Nguyen

IPC: H04L1/06 ,  H03K19/00 ,  H04L25/03

Abstract: An apparatus includes first and second receiver circuits and a decision circuit. The first receiver circuit is configured to generate a first data symbol from a particular input data symbol of a plurality of input data symbols included in an input signal. The second receiver circuit is configured to generate a second data symbol from the particular input data symbol. The decision circuit is configured to select, using respective values of one or more previous output data symbols, either the first or second data symbol as a current output data symbol. In response to a change in value between successive input data symbols, the first and second receiver circuits are configured to generate the first and second data symbols with respective data valid windows with different durations.