公开(公告)号：US11886877B1

公开(公告)日：2024-01-30

申请号：US17548794

申请日：2021-12-13

Applicant: Apple Inc.

Inventor： Richard T. Witek ,  Peter C. Eastty ,  Rajarshi Mukherjee

IPC: G06F9/30 ,  G06F12/02 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/30101 ,  G06F9/3806 ,  G06F12/0238 ,  G06F2212/7201

Abstract: A processor may include a plurality of data memories storing operands that may be operated upon by the processor. Load/store operations may specify a memory location in one of the data memories to be accessed using a memory select value that selects the data memory and an address within the selected data memory. The memory select values may be mapped from virtual memory select values associated with the load/store operations to physical memory select values that may be used to access the data memory.

公开(公告)号：US10243581B1

公开(公告)日：2019-03-26

申请号：US15925705

申请日：2018-03-19

Applicant: Apple Inc.

Inventor： Richard T. Witek ,  Peter C. Eastty

IPC: H03M3/00

Abstract: A method and apparatus for implementing FIR filters in a processor includes a plurality of execution units executing instructions of an instruction set. The execution units include a number of FIR filter circuits, each of which is associated with a corresponding one of a number FIR filter instructions. Furthermore, each of the FIR filter circuits is and dedicated exclusively to executing its corresponding one of the FIR filter instructions. Each FIR filter execution unit receives input data and provides filtered output data.

公开(公告)号：US20200012518A1

公开(公告)日：2020-01-09

申请号：US16029155

申请日：2018-07-06

Applicant: Apple Inc.

Inventor： Richard T. Witek ,  Peter C. Eastty

IPC: G06F9/48

Abstract: A hardware scheduling circuit may receive priority indications for a plurality of threads for processing, by an execution unit, multiple data samples associated with a signal. A particular thread of the plurality of threads may be scheduled for execution by the execution unit based on a priority of the particular thread and based on an availability of some of the multiple data samples that are to be processed by the particular thread.

公开(公告)号：US10691490B2

公开(公告)日：2020-06-23

申请号：US16029155

申请日：2018-07-06

Applicant: Apple Inc.

Inventor： Richard T. Witek ,  Peter C. Eastty

IPC: G06F9/46 ,  G06F9/48

Abstract: A hardware scheduling circuit may receive priority indications for a plurality of threads for processing, by an execution unit, multiple data samples associated with a signal. A particular thread of the plurality of threads may be scheduled for execution by the execution unit based on a priority of the particular thread and based on an availability of some of the multiple data samples that are to be processed by the particular thread.

公开(公告)号：US10564931B1

公开(公告)日：2020-02-18

申请号：US15946428

申请日：2018-04-05

Applicant: Apple Inc.

Inventor： Richard T. Witek ,  Brian D. Clark ,  Peter C. Eastty

IPC: G06F7/499 ,  G06F7/483 ,  G06F9/30

Abstract: In various embodiments, a floating-point arithmetic circuit includes a range exception detection circuit and an output circuit. The range exception detection circuit may generate a selection signal that indicates whether a floating-point arithmetic result generated within the floating-point arithmetic circuit is within a specified range. The output circuit may output the floating-point arithmetic result in response to the selection signal indicating the floating-point arithmetic result is within a specified range. The output circuit may output a corresponding specified value in response to the selection signal indicating the floating-point arithmetic result is not within the specified range. Accordingly, floating-point arithmetic operations may be performed in combination with an operation that limits a range of an output to a specified range.