公开(公告)号：US20240104280A1

公开(公告)日：2024-03-28

申请号：US18471083

申请日：2023-09-20

Applicant: Apple Inc.

Inventor： Peter A. Lisherness ,  Lior Zimet

IPC: G06F30/347

CPC classification number: G06F30/347

Abstract: An integrated circuit (IC) configurable for use in one of a number of possible platforms is disclosed. The IC includes a number of different functional circuit blocks and a plurality of programmable register. The programmable registers, when programmed, can cause corresponding functional circuit blocks to be fully or partially disabled. The different platforms support different sets of peripherals. The IC is thus configured, using the programmable registers, for use in a particular platform to support its corresponding set of peripherals, while another instance of the IC may be configured for use in another platform, supporting its particular set of peripherals.

公开(公告)号：US20250094564A1

公开(公告)日：2025-03-20

申请号：US18790765

申请日：2024-07-31

Applicant: Apple Inc.

Inventor： Peter A. Lisherness ,  Assaf Menachem ,  Assaf Metuki ,  Benjamin Biron ,  D J Capelis ,  Husam Khashiboun ,  Jacques Fortier

IPC: G06F21/53 ,  G06F21/62

Abstract: Techniques are disclosed relating to securing hardware accelerators used by a computing device. In some embodiments, a computing device includes a sensor and sensor processor circuitry coupled to the sensor. The sensor processor circuitry is configured to process sensor data received from a sensor of the computing device. In response to a first indication that a first consumer is trustworthy, the sensor processor circuitry is configured to provide a first data set of the processed sensor data to the first consumer. In response to a second indication that a second consumer is untrustworthy, the sensor processor circuitry is configured to negotiate one or more conditions in which the second consumer is permitted to receive a second data set of the processed sensor data.

公开(公告)号：US20250094565A1

公开(公告)日：2025-03-20

申请号：US18790895

申请日：2024-07-31

Applicant: Apple Inc.

Inventor： Peter A. Lisherness ,  Assaf Menachem ,  Assaf Metuki ,  Benjamin Biron ,  D J Capelis ,  Husam Khashiboun ,  Jacques Fortier

IPC: G06F21/53 ,  G06F21/62

Abstract: Techniques are disclosed relating to securing hardware accelerators used by a computing device. In some embodiments, a computing device includes user interface and user interface pipeline circuitry coupled to the user interface. The user interface pipeline circuitry is configured to process a set of data received from a first source to produce an output for the user interface of the computing device, receive, from a second source, an indication that a component of the computing device has been activated, and, prior to presenting the output via the user interface, insert, into the output, an indicator of the component being activated.

公开(公告)号：US12061855B2

公开(公告)日：2024-08-13

申请号：US18471083

申请日：2023-09-20

Applicant: Apple Inc.

Inventor： Peter A. Lisherness ,  Lior Zimet

IPC: G06F30/347

CPC classification number: G06F30/347

Abstract: An integrated circuit (IC) configurable for use in one of a number of possible platforms is disclosed. The IC includes a number of different functional circuit blocks and a plurality of programmable register. The programmable registers, when programmed, can cause corresponding functional circuit blocks to be fully or partially disabled. The different platforms support different sets of peripherals. The IC is thus configured, using the programmable registers, for use in a particular platform to support its corresponding set of peripherals, while another instance of the IC may be configured for use in another platform, supporting its particular set of peripherals.

公开(公告)号：US20250094563A1

公开(公告)日：2025-03-20

申请号：US18790529

申请日：2024-07-31

Applicant: Apple Inc.

Inventor： Peter A. Lisherness ,  Assaf Menachem ,  Assaf Metuki ,  Benjamin Biron ,  D J Capelis ,  Husam Khashiboun ,  Jacques Fortier ,  Kenneth W. Waters

IPC: G06F21/53 ,  G06F21/54

Abstract: Techniques are disclosed relating to securing hardware accelerators used by a computing device. In some embodiments, a computing device includes one or more processors configured to co-execute trusted processes and untrusted processes in an isolated manner that includes implementing a secure environment in which a set of security criteria is enforced for data of the trusted processes. The computing device further includes multiple heterogenous hardware accelerators configured to implement exclaves of the secure environment that extend enforcement of one or more of the set of security criteria within the hardware accelerators for data distributed to the hardware accelerators for performance of tasks associated with the trusted processes.

公开(公告)号：US12079144B1

公开(公告)日：2024-09-03

申请号：US18054280

申请日：2022-11-10

Applicant: Apple Inc.

Inventor： Sebastian Werner ,  Amir Kleen ,  Jeonghee Shin ,  Peter A. Lisherness

IPC: G06F13/16 ,  G06F13/374

CPC classification number: G06F13/1642 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/374

Abstract: An apparatus includes a communication bus circuit, a memory circuit, a queue manager circuit, and an arbitration circuit. The communication bus circuit includes a command bus and a data bus separate from the command bus. The queue manager circuit may be configured to receive a first memory request and a second memory request, each request including a respective address value to be sent via the command bus. The first memory request may include a corresponding data operand to be sent via the data bus. The queue manager circuit may also be configured to distribute the first memory request and the second memory request among a plurality of bus queues. Distribution of the first and second memory requests may be based on the respective address values. The arbitration circuit may be configured to select a particular memory request from a particular one of the plurality of bus queues.

公开(公告)号：US20240103074A1

公开(公告)日：2024-03-28

申请号：US18471096

申请日：2023-09-20

Applicant: Apple Inc.

Inventor： Peter A. Lisherness ,  Lior Zimet

IPC: G01R31/317 ,  G01R31/319

CPC classification number: G01R31/31724 ,  G01R31/31721 ,  G01R31/31908

Abstract: A configurable computer system is disclosed. The computer system includes a set of processing blocks and a set of programmable registers. A given one of the programmable registers corresponds to at least one of the processing blocks. The computer system is configured to receive a harvesting command that writes a disable value to a group of the programmable registers corresponding to a group of the set of processing blocks to be disabled for a selected computing platform of a plurality of different computing platforms. One or more hardware circuits are configured to perform tasks after a given boot of the computer system, the more tasks utilizing circuitry in the group of the set of processing blocks. A power control circuit is configured to, after tasks have been performed, temporarily disable the group of the set of processing blocks, thereby configuring the computer system for the selected computing platform.