公开(公告)号：US10324844B2

公开(公告)日：2019-06-18

申请号：US15389047

申请日：2016-12-22

Applicant: Apple Inc.

Inventor： Anthony P. DeLaurier ,  Owen C. Anderson ,  Michael J. Swift ,  Aaftab A. Munshi ,  Terence M. Potter

IPC: G09G5/36 ,  G06F12/0815 ,  G06F12/0811 ,  G06F12/084 ,  G06T1/60

Abstract: Techniques are disclosed relating to memory consistency in a memory hierarchy with relaxed ordering. In some embodiments, an apparatus includes a first level cache that is shared by a plurality of shader processing elements and a second level cache that is shared by the shader processing elements and at least a texture processing unit. In some embodiments, the apparatus is configured to execute operations specified by graphics instructions that include (1) an attribute of the operation that specifies a type of memory consistency to be imposed for the operation and (2) scope information for the attribute that specifies whether the memory consistency specified by the attribute should be enforced at the first level cache or the second level cache. In some embodiments, the apparatus is configured to determine whether to sequence memory accesses at the first level cache and the second level cache based on the attribute and the scope.

公开(公告)号：US20180181489A1

公开(公告)日：2018-06-28

申请号：US15389047

申请日：2016-12-22

Applicant: Apple Inc.

Inventor： Anthony P. DeLaurier ,  Owen C. Anderson ,  Michael J. Swift ,  Aaftab A. Munshi ,  Terence M. Potter

IPC: G06F12/0815 ,  G06F12/0811 ,  G06F12/084

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/084 ,  G06F2212/455 ,  G06F2212/621 ,  G06T1/60

Abstract: Techniques are disclosed relating to memory consistency in a memory hierarchy with relaxed ordering. In some embodiments, an apparatus includes a first level cache that is shared by a plurality of shader processing elements and a second level cache that is shared by the shader processing elements and at least a texture processing unit. In some embodiments, the apparatus is configured to execute operations specified by graphics instructions that include (1) an attribute of the operation that specifies a type of memory consistency to be imposed for the operation and (2) scope information for the attribute that specifies whether the memory consistency specified by the attribute should be enforced at the first level cache or the second level cache. In some embodiments, the apparatus is configured to determine whether to sequence memory accesses at the first level cache and the second level cache based on the attribute and the scope.