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公开(公告)号：US20190006287A1
公开(公告)日：2019-01-03
申请号：US15636408
申请日：2017-06-28
Applicant: Apple Inc.
Inventor： Paul A. Martinez , Ming Y. Tsai , Won Seop Choi
IPC: H01L23/552 , H01L49/02
CPC classification number: H01L23/552 , H01G4/12 , H01G4/232 , H01G4/248 , H01G4/30 , H01L23/642 , H01L28/60
Abstract: Capacitor devices having multiple capacitors with similar nominal capacitances are described. The capacitors may be multilayer ceramic capacitors (MLCCs) and may be fabricated employing class 2 materials. The arrangement of the electrodes in the device may reduce relative variations between the capacitors of the device. The capacitor devices may be allow high performance and compact electrical circuits that may employ matched capacitors.
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公开(公告)号：US20170207024A1
公开(公告)日：2017-07-20
申请号：US15409217
申请日：2017-01-18
Applicant: Apple Inc.
Inventor： Paul A. Martinez , Gang Ning , Curtis C. Mead , Ming Y. Tsai , Albert Wang
CPC classification number: H01G4/30 , H01G2/06 , H01G4/012 , H01G4/12 , H01G4/232 , H01G4/35 , H01G4/40
Abstract: Methods and devices related to fabrication and utilization of multilayer capacitors presenting low equivalent series resistance (ESR) is illustrated. The capacitors may present electrodes that are coupled to metallic terminations at the bottom and/or at the side of the capacitor. The position of the electrode coupling may lead to smaller current paths in the MLCC electrode, which may decrease line inductances. Methods and systems for fabrication of the capacitors described are also discussed.
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公开(公告)号：US20190096581A1
公开(公告)日：2019-03-28
申请号：US15717431
申请日：2017-09-27
Applicant: Apple Inc.
Inventor： Behzad Reyhani Masoleh , Ming Y. Tsai , Paul A. Martinez , Scott D. Morrison , Tracey L. Chavers
CPC classification number: H01G4/248 , H01G2/22 , H01G4/002 , H01G4/005 , H01G4/224 , H01G4/232 , H01G4/30 , H05K1/0216 , H05K1/111 , H05K1/181 , H05K3/34 , H05K2201/10015 , H05K2201/10371
Abstract: Capacitor devices with electrodes that are geometrically arranged to reduce parasitic capacitances are described. The capacitors may be multilayer ceramic capacitor (MLCC) structures in which certain electrodes may have a clearance from a capacitor structure wall, such as top wall. In circuits and devices where that particular capacitor wall may be placed near a shielding structure, the clearance may reduce unintended parasitic capacitances between the shield structure and the electrodes. As a result, the shield structures may be placed closer to the electronic components, which may allow circuit boards and electronic devices with a lower profile.
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公开(公告)号：US20180068784A1
公开(公告)日：2018-03-08
申请号：US15405027
申请日：2017-01-12
Applicant: Apple Inc.
Inventor： Paul A. Martinez , Ming Y. Tsai , Federico P. Centola , Martin Schauer , Cheung-Wei Lam , Jason C. Sauers
CPC classification number: H01F27/365 , H01F17/0013 , H01F2017/008 , H05K1/023 , H05K1/18
Abstract: A system includes a circuit board, an inductor including windings mounted on the circuit board, and a plurality of magnetic field containment devices. Each magnetic field containment device includes an independent electrical circuit that is not directly electrically connected via a conductor to any other magnetic field containment device. Each magnetic field containment device also includes a material of a certain relative permeability. Each magnetic field containment device at least partially surrounds the inductor and, in operation, at least partially contains a magnetic B-Field generated by electrical current in the windings of the inductor. The plurality of magnetic field containment devices, in operation, enables a certain saturation current in the inductor.
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Patent Agency Ranking
公开(公告)号：US10510492B2
公开(公告)日：2019-12-17
申请号：US15600329
申请日：2017-05-19
Applicant: Apple Inc.
Inventor： Ming Y. Tsai , Albert Wang , Curtis C. Mead , Tyler S. Bushnell , Paul A. Martinez
Abstract: Monolithic capacitor structures having a main capacitor and a vise capacitor are discussed. The vise capacitor provides to the monolithic capacitor structure reduced vibrations and/or acoustic noise due to piezoelectric effects. To that end, vise capacitor may cause piezoelectric deformations that compensate the deformations that are caused by the electrical signals in the main capacitor. Embodiments of these capacitor structures may have the main capacitor and the vise capacitor sharing portions of a rigid dielectric. Electrical circuitry that employs the vise capacitor to reduce noise and/or vibration in the monolithic capacitor structures is also described. Methods for fabrication of these capacitors are discussed as well.
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公开(公告)号：US10461040B2
公开(公告)日：2019-10-29
申请号：US15636408
申请日：2017-06-28
Applicant: Apple Inc.
Inventor： Paul A. Martinez , Ming Y. Tsai , Won Seop Choi
Abstract: Capacitor devices having multiple capacitors with similar nominal capacitances are described. The capacitors may be multilayer ceramic capacitors (MLCCs) and may be fabricated employing class 2 materials. The arrangement of the electrodes in the device may reduce relative variations between the capacitors of the device. The capacitor devices may be allow high performance and compact electrical circuits that may employ matched capacitors.
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公开(公告)号：US10332683B2
公开(公告)日：2019-06-25
申请号：US15717431
申请日：2017-09-27
Applicant: Apple Inc.
Inventor： Behzad Reyhani Masoleh , Ming Y. Tsai , Paul A. Martinez , Scott D. Morrison , Tracey L. Chavers
IPC: H01G4/248 , H01G4/30 , H01G4/002 , H01G4/224 , H05K1/02 , H05K1/18 , H05K1/11 , H01G4/232 , H05K3/34
Abstract: Capacitor devices with electrodes that are geometrically arranged to reduce parasitic capacitances are described. The capacitors may be multilayer ceramic capacitor (MLCC) structures in which certain electrodes may have a clearance from a capacitor structure wall, such as top wall. In circuits and devices where that particular capacitor wall may be placed near a shielding structure, the clearance may reduce unintended parasitic capacitances between the shield structure and the electrodes. As a result, the shield structures may be placed closer to the electronic components, which may allow circuit boards and electronic devices with a lower profile.
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公开(公告)号：US10256036B2
公开(公告)日：2019-04-09
申请号：US15405027
申请日：2017-01-12
Applicant: Apple Inc.
Inventor： Paul A. Martinez , Ming Y. Tsai , Federico P. Centola , Martin Schauer , Cheung-Wei Lam , Jason C. Sauers
Abstract: A system includes a circuit board, an inductor including windings mounted on the circuit board, and a plurality of magnetic field containment devices. Each magnetic field containment device includes an independent electrical circuit that is not directly electrically connected via a conductor to any other magnetic field containment device. Each magnetic field containment device also includes a material of a certain relative permeability. Each magnetic field containment device at least partially surrounds the inductor and, in operation, at least partially contains a magnetic B-Field generated by electrical current in the windings of the inductor. The plurality of magnetic field containment devices, in operation, enables a certain saturation current in the inductor.
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公开(公告)号：US20180337003A1
公开(公告)日：2018-11-22
申请号：US15600329
申请日：2017-05-19
Applicant: Apple Inc.
Inventor： Ming Y. Tsai , Albert Wang , Curtis C. Mead , Tyler S. Bushnell , Paul A. Martinez
IPC: H01G4/35 , H01G4/12 , H01G4/005 , H01G4/30 , H01L41/047
Abstract: Monolithic capacitor structures having a main capacitor and a vise capacitor are discussed. The vise capacitor provides to the monolithic capacitor structure reduced vibrations and/or acoustic noise due to piezoelectric effects. To that end, vise capacitor may cause piezoelectric deformations that compensate the deformations that are caused by the electrical signals in the main capacitor. Embodiments of these capacitor structures may have the main capacitor and the vise capacitor sharing portions of a rigid dielectric. Electrical circuitry that employs the vise capacitor to reduce noise and/or vibration in the monolithic capacitor structures is also described. Methods for fabrication of these capacitors are discussed as well.
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