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公开(公告)号：US20200053729A1
公开(公告)日：2020-02-13
申请号：US16532995
申请日：2019-08-06
Applicant: Apple Inc.
Inventor： Daniel R. Borges , Oren Shani , Christiaan A. Hartman , Yong Liu , Charles F. Dominguez , Karthik R. Mekala , Tashbeeb Haque , Lawrie Kurian , Mete Fikirlier , Guoqing Li , Rajneesh Kumar , Ka Ho P. Poon , Brian B. Whitaker , Joseph Hakim , John A. Wilson , Tony Chi Wang Ng , Roopkumar Parthasarathy Rao , Curtis J. Schmidek , Shishir Gupta , Tushar R. Shah , Jacob H. Power , Bryan J. Follis , Anand Rajagopalan
Abstract: An interface circuit in an electronic device may contend for access to a shared communication channel on behalf of the electronic device and a recipient electronic device, where the access has a duration. Then, the electronic device may provide a schedule frame intended for the recipient electronic device that includes information that specifies one or more time slots during the duration that are associated with the recipient electronic device and one or more communication functions of the recipient electronic device in the one or more time slots. Moreover, the electronic device may provide a data frame with data intended for the recipient electronic device. In response, the electronic device may receive a response frame associated with the recipient electronic device, where the response frame is received during at least one of the one or more time slots.
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公开(公告)号：US10372158B2
公开(公告)日：2019-08-06
申请号：US15706570
申请日：2017-09-15
Applicant: Apple Inc.
Inventor： Charles Dominguez , Mete Fikirlier
Abstract: A device implementing an inter-chip time synchronization system may include a first circuit having a first clock and a second circuit having a second clock. The first circuit may be configured to capture a first timestamp from the first clock responsive to receiving a sampling signal from the second circuit. The first circuit may be configured to receive a second timestamp that was captured by the second circuit from a second clock of the second circuit. The second timestamp may have been captured by the second circuit when the sampling signal was transmitted to the first circuit. The first circuit may be configured to generate a conversion parameter for converting from the second clock of the second circuit to the first clock of the first circuit based at least in part on the first and second timestamps, and to store the generated conversion parameter.
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公开(公告)号：US11184890B2
公开(公告)日：2021-11-23
申请号：US16532995
申请日：2019-08-06
Applicant: Apple Inc.
Inventor： Daniel R. Borges , Oren Shani , Christiaan A. Hartman , Yong Liu , Charles F. Dominguez , Karthik R. Mekala , Tashbeeb Haque , Lawrie Kurian , Mete Fikirlier , Guoqing Li , Rajneesh Kumar , Ka Ho P. Poon , Brian B. Whitaker , Joseph Hakim , John A. Wilson , Tony Chi Wang Ng , Roopkumar Parthasarathy Rao , Curtis J. Schmidek , Shishir Gupta , Tushar R. Shah , Jacob H. Power , Bryan J. Follis , Anand Rajagopalan
Abstract: An interface circuit in an electronic device may contend for access to a shared communication channel on behalf of the electronic device and a recipient electronic device, where the access has a duration. Then, the electronic device may provide a schedule frame intended for the recipient electronic device that includes information that specifies one or more time slots during the duration that are associated with the recipient electronic device and one or more communication functions of the recipient electronic device in the one or more time slots. Moreover, the electronic device may provide a data frame with data intended for the recipient electronic device. In response, the electronic device may receive a response frame associated with the recipient electronic device, where the response frame is received during at least one of the one or more time slots.
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公开(公告)号：US11770731B2
公开(公告)日：2023-09-26
申请号：US16555356
申请日：2019-08-29
Applicant: Apple Inc.
Inventor： Guoqing Li , Yang Yu , Welly Kasten , Shehla S. Rana , Mete Fikirlier , Karthik R. Mekala , Charles F. Dominguez , Yong Liu , Rajneesh Kumar
CPC classification number: H04W28/0221 , H04W52/0216 , H04W52/0229 , H04W52/0206
Abstract: Some embodiments of this disclosure include apparatuses and methods for implementing a target wake time (TWT) scheme that includes traffic differentiation and service period extension. For example some embodiments relate to an electronic device including a transceiver and one or more processors communicatively coupled to the transceiver. The one or more processors receive an indication of traffic associated with an application. The one or more processors determine information associated with the traffic and configure the TWT scheme associated with the traffic based at least in part on the determined information. The one or more processors further communicate initial information associated with the TWT scheme to an access point of a wireless network. The initial information associated with the TWT scheme can include at least one of traffic direction information, traffic pattern information, a traffic identifier (TID), or an access category, indication (ACID).
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