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公开(公告)号：US20160182047A1
公开(公告)日：2016-06-23
申请号：US14705479
申请日：2015-05-06
Applicant: Apple Inc.
Inventor： Gary L. Stirk , Karthik Kadirvel
IPC: H03K19/0175
CPC classification number: H03K19/017509 , G01R31/3655 , G01R31/3675 , G06F13/4256 , H02J7/0021 , H02J7/0026 , H02J7/0052 , H02J7/0068 , H02J7/007 , H02J2007/0059 , H03L7/00 , Y02D10/14 , Y02D10/151
Abstract: A system may include a plurality of units, wherein each unit has a respective common mode voltage terminal, communication up terminal, and communication down terminal. A first unit of the plurality of units may be configured to generate a first plurality of currents on its communication up terminal, wherein the first plurality of currents corresponds to a first plurality of bits. A second unit of the plurality of units may be configured to receive the first plurality of currents on its respective communication down terminal, and maintain a voltage level at its respective communication down terminal during reception of the first plurality of currents. The voltage level may be equal to a common mode voltage of the respective common mode voltage terminal of the second unit.
Abstract translation: 系统可以包括多个单元，其中每个单元具有相应的共模电压端子，通信上行端子和通信下降端子。 多个单元中的第一单元可以被配置为在其通信上行终端上产生第一多个电流，其中第一多个电流对应于第一多个位。 多个单元中的第二单元可以被配置为在其各自的通信下行终端接收第一多个电流，并且在接收第一多个电流期间在其各自的通信下行端子处保持电压电平。 电压电平可以等于第二单元的各个共模电压端子的共模电压。
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公开(公告)号：US09813063B2
公开(公告)日：2017-11-07
申请号：US14705600
申请日：2015-05-06
Applicant: Apple Inc.
Inventor： Gary L. Stirk , Karthik Kadirvel
IPC: H03K19/0175 , G01R31/36 , H02J7/00 , H03L7/00 , G06F13/42
CPC classification number: H03K19/017509 , G01R31/3655 , G01R31/3675 , G06F13/4256 , H02J7/0021 , H02J7/0026 , H02J7/0052 , H02J7/0068 , H02J7/007 , H02J2007/0059 , H03L7/00 , Y02D10/14 , Y02D10/151
Abstract: An apparatus may include one or more registers configured to store a plurality of values, and an analog-to-digital converter (ADC). Each value of the plurality of values may correspond to a characteristic of a transistor at a respective temperature value. The ADC may be configured to generate a digital value corresponding to a difference in voltage levels between a first terminal and a second terminal of the transistor. The apparatus may further include a sensor configured to measure a temperature, and control logic configured to generate a first voltage level at a control terminal of the transistor and receive the digital value from the ADC. The control logic may be further configured to determine, during a first operational mode, a current passing through the transistor dependent upon the digital value, at least one value of the plurality of values, and the temperature.
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公开(公告)号：US09413359B2
公开(公告)日：2016-08-09
申请号：US14743174
申请日：2015-06-18
Applicant: Apple Inc.
Inventor： Gary L. Stirk
CPC classification number: H03K19/017509 , G01R31/3655 , G01R31/3675 , G06F13/4256 , H02J7/0021 , H02J7/0026 , H02J7/0052 , H02J7/0068 , H02J7/007 , H02J2007/0059 , H03L7/00 , Y02D10/14 , Y02D10/151
Abstract: A system may include a plurality of devices, wherein each device of the plurality of devices has a respective clock source. A first device of the plurality of devices may be configured to generate a first clock signal. A second device of the plurality of devices may be configured to generate a second clock signal, receive the first clock signal from the first device, and modify a first frequency of the first clock signal. The second device may be further configured to adjust a second frequency of the second clock signal dependent upon the modified first frequency of the first clock signal.
Abstract translation: 系统可以包括多个设备，其中多个设备中的每个设备具有相应的时钟源。 多个设备中的第一设备可以被配置为产生第一时钟信号。 多个设备中的第二设备可以被配置为产生第二时钟信号，从第一设备接收第一时钟信号，并修改第一时钟信号的第一频率。 第二装置还可以被配置为根据第一时钟信号的修改的第一频率来调整第二时钟信号的第二频率。
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公开(公告)号：US20160182058A1
公开(公告)日：2016-06-23
申请号：US14743174
申请日：2015-06-18
Applicant: Apple Inc.
Inventor： Gary L. Stirk
IPC: H03L7/00
CPC classification number: H03K19/017509 , G01R31/3655 , G01R31/3675 , G06F13/4256 , H02J7/0021 , H02J7/0026 , H02J7/0052 , H02J7/0068 , H02J7/007 , H02J2007/0059 , H03L7/00 , Y02D10/14 , Y02D10/151
Abstract: A system may include a plurality of devices, wherein each device of the plurality of devices has a respective clock source. A first device of the plurality of devices may be configured to generate a first clock signal. A second device of the plurality of devices may be configured to generate a second clock signal, receive the first clock signal from the first device, and modify a first frequency of the first clock signal. The second device may be further configured to adjust a second frequency of the second clock signal dependent upon the modified first frequency of the first clock signal.
Abstract translation: 系统可以包括多个设备，其中多个设备中的每个设备具有相应的时钟源。 多个设备中的第一设备可以被配置为产生第一时钟信号。 多个设备中的第二设备可以被配置为产生第二时钟信号，从第一设备接收第一时钟信号，并修改第一时钟信号的第一频率。 第二装置还可以被配置为根据第一时钟信号的修改的第一频率来调整第二时钟信号的第二频率。
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5.发明申请APPARATUS FOR A REDUCED CURRENT WAKE-UP CIRCUIT FOR A BATTERY MANAGEMENT SYSTEM 有权一种用于电池管理系统的减少电流唤醒电路的装置公开(公告)号：US20160181846A1
公开(公告)日：2016-06-23
申请号：US14705553
申请日：2015-05-06
Applicant: Apple Inc.
Inventor： Gary L. Stirk
IPC: H02J7/00
CPC classification number: H03K19/017509 , G01R31/3655 , G01R31/3675 , G06F13/4256 , H02J7/0021 , H02J7/0026 , H02J7/0052 , H02J7/0068 , H02J7/007 , H02J2007/0059 , H03L7/00 , Y02D10/14 , Y02D10/151
Abstract: An apparatus may include an energy monitoring circuit configured to generate a bitstream dependent upon an amount of charge passing through a sensing unit. The apparatus may also include a control unit configured to receive the bitstream from the energy monitoring circuit, and modify a count value in response to a determined state of each bit of the bitstream. The control unit may also read a first value of the count value at a first time and at a later second time read a second value of the count value. The control unit may assert a wake-up signal in response to a determination that a difference between the first value and the second value is greater than a predetermined threshold value.
Abstract translation: 装置可以包括能量监测电路，其被配置为根据通过感测单元的电荷量产生比特流。 该装置还可以包括控制单元，其被配置为从能量监视电路接收比特流，并且响应于比特流的每个比特的确定状态来修改计数值。 控制单元还可以在第一时间和稍后的第二时间读取计数值的第一值，读取计数值的第二值。 响应于第一值和第二值之间的差大于预定阈值的确定，控制单元可以断言唤醒信号。
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Patent Agency Ranking
公开(公告)号：US10236694B2
公开(公告)日：2019-03-19
申请号：US15662408
申请日：2017-07-28
Applicant: Apple Inc.
Inventor： Thomas C. Greening , Karthik Kadirvel , Gary L. Stirk , Saroj K. Sahu , Kamran M. Hasan
Abstract: This disclosure describes a battery pack that includes a plurality of asymmetrical banks, with different capacities and/or voltages, and multiple taps, coupled to the corresponding banks, to power electrical loads. The battery pack also comprise a balancing circuit and a battery management unit. The battery pack may regulate voltages among the banks and/or balance the states of charge among the asymmetrical banks, by moving charges among the banks, by controlling one or more converters. The battery pack monitors the status of its banks and communicate with a host system via the battery management unit. Based on the monitored information and/or communication, the battery management unit generates control signals to drive the one or more converters.
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公开(公告)号：US20180034288A1
公开(公告)日：2018-02-01
申请号：US15662408
申请日：2017-07-28
Applicant: Apple Inc.
Inventor： Thomas C. Greening , Karthik Kadirvel , Gary L. Stirk , Saroj K. Sahu , Kamran M. Hasan
IPC: H02J7/00
CPC classification number: H02J7/0019 , H01M10/425 , H01M10/441 , H01M2010/4271 , H02J7/0022 , H02J7/0026 , H02J7/0077 , H02J2007/0098
Abstract: This disclosure describes a battery pack that includes a plurality of asymmetrical banks, with different capacities and/or voltages, and multiple taps, coupled to the corresponding banks, to power electrical loads. The battery pack also comprise a balancing circuit and a battery management unit. The battery pack may regulate voltages among the banks and/or balance the states of charge among the asymmetrical banks, by moving charges among the banks, by controlling one or more converters. The battery pack monitors the status of its banks and communicate with a host system via the battery management unit. Based on the monitored information and/or communication, the battery management unit generates control signals to drive the one or more converters.
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公开(公告)号：US09680471B2
公开(公告)日：2017-06-13
申请号：US14705553
申请日：2015-05-06
Applicant: Apple Inc.
Inventor： Gary L. Stirk
IPC: H02J7/00 , H03K19/0175 , G01R31/36 , H03L7/00 , G06F13/42
CPC classification number: H03K19/017509 , G01R31/3655 , G01R31/3675 , G06F13/4256 , H02J7/0021 , H02J7/0026 , H02J7/0052 , H02J7/0068 , H02J7/007 , H02J2007/0059 , H03L7/00 , Y02D10/14 , Y02D10/151
Abstract: An apparatus may include an energy monitoring circuit configured to generate a bitstream dependent upon an amount of charge passing through a sensing unit. The apparatus may also include a control unit configured to receive the bitstream from the energy monitoring circuit, and modify a count value in response to a determined state of each bit of the bitstream. The control unit may also read a first value of the count value at a first time and at a later second time read a second value of the count value. The control unit may assert a wake-up signal in response to a determination that a difference between the first value and the second value is greater than a predetermined threshold value.
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公开(公告)号：US09413354B2
公开(公告)日：2016-08-09
申请号：US14705479
申请日：2015-05-06
Applicant: Apple Inc.
Inventor： Gary L. Stirk , Karthik Kadirvel
IPC: H03K5/08 , H03K19/0175
CPC classification number: H03K19/017509 , G01R31/3655 , G01R31/3675 , G06F13/4256 , H02J7/0021 , H02J7/0026 , H02J7/0052 , H02J7/0068 , H02J7/007 , H02J2007/0059 , H03L7/00 , Y02D10/14 , Y02D10/151
Abstract: A system may include a plurality of units, wherein each unit has a respective common mode voltage terminal, communication up terminal, and communication down terminal. A first unit of the plurality of units may be configured to generate a first plurality of currents on its communication up terminal, wherein the first plurality of currents corresponds to a first plurality of bits. A second unit of the plurality of units may be configured to receive the first plurality of currents on its respective communication down terminal, and maintain a voltage level at its respective communication down terminal during reception of the first plurality of currents. The voltage level may be equal to a common mode voltage of the respective common mode voltage terminal of the second unit.
Abstract translation: 系统可以包括多个单元，其中每个单元具有相应的共模电压端子，通信上行端子和通信下降端子。 多个单元中的第一单元可以被配置为在其通信上行终端上产生第一多个电流，其中第一多个电流对应于第一多个位。 多个单元中的第二单元可以被配置为在其各自的通信下行终端接收第一多个电流，并且在接收第一多个电流期间在其各自的通信下行端子处保持电压电平。 电压电平可以等于第二单元的各个共模电压端子的共模电压。
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10.发明申请公开(公告)号：US20160178705A1
公开(公告)日：2016-06-23
申请号：US14705600
申请日：2015-05-06
Applicant: Apple Inc.
Inventor： Gary L. Stirk , Karthik Kadirvel
CPC classification number: H03K19/017509 , G01R31/3655 , G01R31/3675 , G06F13/4256 , H02J7/0021 , H02J7/0026 , H02J7/0052 , H02J7/0068 , H02J7/007 , H02J2007/0059 , H03L7/00 , Y02D10/14 , Y02D10/151
Abstract: An apparatus may include one or more registers configured to store a plurality of values, and an analog-to-digital converter (ADC). Each value of the plurality of values may correspond to a characteristic of a transistor at a respective temperature value. The ADC may be configured to generate a digital value corresponding to a difference in voltage levels between a first terminal and a second terminal of the transistor. The apparatus may further include a sensor configured to measure a temperature, and control logic configured to generate a first voltage level at a control terminal of the transistor and receive the digital value from the ADC. The control logic may be further configured to determine, during a first operational mode, a current passing through the transistor dependent upon the digital value, at least one value of the plurality of values, and the temperature.
Abstract translation: 装置可以包括被配置为存储多个值的一个或多个寄存器和模数转换器（ADC）。 多个值的每个值可以对应于在相应温度值下的晶体管的特性。 ADC可以被配置为产生对应于晶体管的第一端子和第二端子之间的电压电平差的数字值。 该装置还可以包括被配置为测量温度的传感器和被配置为在晶体管的控制端产生第一电压电平并且从ADC接收数字值的控制逻辑。 控制逻辑可以进一步配置为在第一操作模式期间确定依赖于数字值，多个值中的至少一个值和温度的通过晶体管的电流。
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