-
公开(公告)号:US20230207502A1
公开(公告)日:2023-06-29
申请号:US18117539
申请日:2023-03-06
发明人: Jin Young Kim , Ji Young Chung , Doo Hyun Park , Choon Heung Lee
IPC分类号: H01L23/00 , H01L21/56 , H01L23/31 , H01L23/538 , H01L25/10 , H01L21/683
CPC分类号: H01L24/02 , H01L21/563 , H01L23/3142 , H01L23/5389 , H01L25/105 , H01L21/568 , H01L23/5385 , H01L21/6835 , H01L24/81 , H01L24/16 , H01L2224/023 , H01L2224/02319 , H01L2224/02371 , H01L2224/02373 , H01L2224/0401 , H01L24/73 , H01L2924/15311 , H01L2224/92125 , H01L2224/13124 , H01L24/32 , H01L2224/81001 , H01L2224/81192 , H01L2225/1058 , H01L2221/68372 , H01L2224/16225 , H01L21/4857
摘要: A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form.
-
公开(公告)号:US11600582B2
公开(公告)日:2023-03-07
申请号:US16921522
申请日:2020-07-06
发明人: Jin Young Kim , Ji Young Chung , Doo Hyun Park , Choon Heung Lee
IPC分类号: H01L23/00 , H01L21/56 , H01L23/31 , H01L23/538 , H01L25/10 , H01L21/683 , H01L21/48
摘要: A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form.
-
公开(公告)号:US11424180B2
公开(公告)日:2022-08-23
申请号:US16890624
申请日:2020-06-02
发明人: Jong Sik Paek , Jin Young Kim , YoonJoo Kim , Jin Han Kim , SeungJae Lee , Se Woong Cha , SungKyu Kim , Jae Hun Bae , Dong Jin Kim , Doo Hyun Park
IPC分类号: H01L23/498 , H01L23/00 , H01L23/31 , H01L21/56
摘要: A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include providing a carrier with a non-photosensitive protection layer, forming a pattern in the non-photosensitive protection layer, providing a semiconductor die with a contact pad on a first surface, and bonding the semiconductor die to the non-photosensitive protection layer such that the contact pad aligns with the pattern formed in the non-photosensitive protection layer. A second surface opposite to the first surface of the semiconductor die, side surfaces between the first and second surfaces of the semiconductor die, and a portion of a first surface of the non-photosensitive protection layer may be encapsulated with an encapsulant. The carrier may be removed leaving the non-photosensitive protection layer bonded to the semiconductor die. A redistribution layer may be formed on the contact pad and a second surface of the non-photosensitive protection layer opposite to the first surface.
-
公开(公告)号:US11183493B2
公开(公告)日:2021-11-23
申请号:US16545105
申请日:2019-08-20
发明人: Jin Young Kim , Doo Hyun Park , Ju Hoon Yoon , Seong Min Seo , Glenn Rinne , Choon Heung Lee
IPC分类号: H01L25/065 , H01L25/00 , H01L23/31 , H01L21/56
摘要: Provided are a semiconductor device using, for example, an epoxy molding compound (EMC) wafer support system and a fabricating method thereof, which can, for example, adjust a thickness of the overall package in a final stage of completing the device while shortening a fabricating process and considerably reducing the fabrication cost. An example semiconductor device may comprise a first semiconductor die that comprises a bond pad and a through silicon via (TSV) connected to the bond pad; an interposer comprising a redistribution layer connected to the bond pad or the TSV and formed on the first semiconductor die, a second semiconductor die connected to the redistribution layer of the interposer and positioned on the interposer; an encapsulation unit encapsulating the second semiconductor die, and a solder ball connected to the bond pad or the TSV of the first semiconductor die.
-
公开(公告)号:US11107701B2
公开(公告)日:2021-08-31
申请号:US16740770
申请日:2020-01-13
发明人: Jin Young Kim , Doo Hyun Park , Seung Jae Lee
摘要: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.
-
公开(公告)号:US11961867B2
公开(公告)日:2024-04-16
申请号:US17837702
申请日:2022-06-10
发明人: Jin Young Kim , No Sun Park , Yoon Joo Kim , Seung Jae Lee , Se Woong Cha , Sung Kyu Kim , Ju Hoon Yoon
IPC分类号: H01L27/146 , G06V40/12 , H01L23/00 , H01L23/498 , H01L23/528 , H01L21/56
CPC分类号: H01L27/14636 , H01L23/49811 , H01L23/49827 , H01L23/5286 , H01L24/19 , H01L24/20 , H01L27/14618 , H01L27/14678 , G06V40/12 , H01L21/568 , H01L2224/04105 , H01L2224/211 , H01L2224/214 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2924/181 , H01L2924/00 , H01L2924/12042 , H01L2924/00
摘要: Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 μm or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof.
-
公开(公告)号:US11764078B2
公开(公告)日:2023-09-19
申请号:US17459706
申请日:2021-08-27
发明人: Jin Young Kim , Doo Hyun Park , Seung Jae Lee
CPC分类号: H01L21/486 , H01L21/4853 , H01L21/565 , H01L23/16 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/02 , H01L24/03 , H01L24/19 , H01L24/20 , H01L24/81 , H01L25/105 , H01L24/73 , H01L2224/02371 , H01L2224/02372 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1035 , H01L2225/1058 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2224/48091 , H01L2924/00014 , H01L2224/73265 , H01L2224/32145 , H01L2224/48227 , H01L2924/00012 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00012 , H01L2924/15311 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00 , H01L2924/1461 , H01L2924/00 , H01L2924/181 , H01L2924/00012
摘要: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.
-
公开(公告)号:US20230057803A1
公开(公告)日:2023-02-23
申请号:US17891310
申请日:2022-08-19
发明人: Jong Sik Paek , Jin Young Kim , YoonJoo Kim , Jin Han Kim , SeungJae Lee , Se Woong Cha , SungKyu Kim , Jae Hun Bae , Dong Jin Kim , Doo Hyun Park
IPC分类号: H01L23/498 , H01L23/00 , H01L23/31
摘要: A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include providing a carrier with a non-photosensitive protection layer, forming a pattern in the non-photosensitive protection layer, providing a semiconductor die with a contact pad on a first surface, and bonding the semiconductor die to the non-photosensitive protection layer such that the contact pad aligns with the pattern formed in the non-photosensitive protection layer. A second surface opposite to the first surface of the semiconductor die, side surfaces between the first and second surfaces of the semiconductor die, and a portion of a first surface of the non-photosensitive protection layer may be encapsulated with an encapsulant. The carrier may be removed leaving the non-photosensitive protection layer bonded to the semiconductor die. A redistribution layer may be formed on the contact pad and a second surface of the non-photosensitive protection layer opposite to the first surface.
-
公开(公告)号:US20220375985A1
公开(公告)日:2022-11-24
申请号:US17837702
申请日:2022-06-10
发明人: Jin Young Kim , No Sun Park , Yoon Joo Kim , Seung Jae Lee , Se Woong Cha , Sung Kyu Kim , Ju Hoon Yoon
IPC分类号: H01L27/146 , H01L23/00 , H01L23/498 , H01L23/528
摘要: Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 μm or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof.
-
公开(公告)号:US20220130682A1
公开(公告)日:2022-04-28
申请号:US17459706
申请日:2021-08-27
发明人: Jin Young Kim , Doo Hyun Park , Seung Jae Lee
摘要: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.
-
-
-
-
-
-
-
-
-