公开(公告)号：US11625269B1

公开(公告)日：2023-04-11

申请号：US17301343

申请日：2021-03-31

Applicant: Amazon Technologies, Inc.

Inventor： Robert Geva ,  Taylor Goodhart ,  Ron Diamant ,  Preston Pengra Briggs

IPC: G06F9/48 ,  G06F8/41 ,  G06N3/063 ,  G06F7/24

Abstract: A technique for scheduling instructions includes obtaining a set of instructions that operate on memory objects, and determining the dependencies of the memory objects. The memory objects are then sorted into a sequence of memory objects based on the dependencies of the memory objects, and the set of instructions are scheduled into a sequence of instructions according to the sequence of memory objects. Sorting memory objects allows instructions that operate on the same memory object to be kept together. This helps minimize spilling conditions because intervening instructions that do not operate on the same memory object can be avoided.

公开(公告)号：US11372677B1

公开(公告)日：2022-06-28

申请号：US16892692

申请日：2020-06-04

Applicant: Amazon Technologies, Inc.

Inventor： Robert Geva

IPC: G06F9/38 ,  G06F9/48 ,  G06N3/02 ,  G06F9/30

Abstract: When scheduling instructions for execution on a computing device, load instructions are processed before their dependent computational instructions. This can result in the load instructions being scheduled in a non-optimal order. To schedule the load instructions in a preferred order, a scheduler can speculatively schedule the load instructions without committing to their order. Subsequently, when the scheduler encounters the dependent computational instructions, the scheduler can reorder the speculatively scheduled load instructions according to the execution order of the dependent computational instructions.

公开(公告)号：US12182549B1

公开(公告)日：2024-12-31

申请号：US18230988

申请日：2023-08-07

Applicant: Amazon Technologies, Inc.

Inventor： Preston Pengra Briggs ,  Ron Diamant ,  Robert Geva

IPC: G06F8/41 ,  G06F9/30 ,  G06F12/06

Abstract: A compiler-implemented technique for performing a storage allocation is described. Computer code to be converted into machine instructions for execution on an integrated circuit device is received. The integrated circuit device includes a memory having a set of memory locations. Based on the computer code, a set of values that are to be stored on the integrated circuit device are determined. An interference graph that includes the set of values and a set of interferences is constructed. While traversing the interference graph, a set of memory location assignments are generated by assigning the set of values to the set of memory locations in accordance with one or more color selection schemes.

公开(公告)号：US12131188B1

公开(公告)日：2024-10-29

申请号：US18192081

申请日：2023-03-29

Applicant: Amazon Technologies, Inc.

Inventor： Robert Geva ,  Taylor Goodhart ,  Ron Diamant ,  Preston Pengra Briggs

IPC: G06F9/48 ,  G06F8/41 ,  G06N3/063

CPC classification number: G06F9/4881 ,  G06F8/43 ,  G06F8/433 ,  G06N3/063

Abstract: A technique for scheduling instructions includes obtaining a set of instructions that operate on memory objects, and determining the dependencies of the memory objects. The memory objects are then sorted into a sequence of memory objects based on the dependencies of the memory objects, and the set of instructions are scheduled into a sequence of instructions according to the sequence of memory objects. Sorting memory objects allows instructions that operate on the same memory object to be kept together. This helps minimize spilling conditions because intervening instructions that do not operate on the same memory object can be avoided.

公开(公告)号：US11809849B1

公开(公告)日：2023-11-07

申请号：US17326175

申请日：2021-05-20

Applicant: Amazon Technologies, Inc.

Inventor： Hongbin Zheng ,  Randy Renfu Huang ,  Robert Geva

IPC: G06F9/44 ,  G06F8/41 ,  G06F13/28 ,  G06N3/04 ,  G06F9/38

CPC classification number: G06F8/452 ,  G06F9/3853 ,  G06F13/28 ,  G06N3/04

Abstract: In one example, a method performed by a compiler comprises: receiving a dataflow graph of a neural network, the neural network comprising a neural network operator; receiving information of computation resources and memory resources of a neural network hardware accelerator intended to execute the neural network operator; determining, based on the dataflow graph, iterations of an operation on elements of a tensor included in the neural network operator; determining, based on the information, a mapping between the elements of the tensor to addresses in the portion of the local memory, and a number of the iterations of the operation to be included in a batch, wherein the number of the iterations in the batch are to be executed in parallel by the neural network hardware accelerator; and generating a schedule of execution of the batches of the iterations of the operations.

公开(公告)号：US11775268B1

公开(公告)日：2023-10-03

申请号：US17341762

申请日：2021-06-08

Applicant: Amazon Technologies, Inc.

Inventor： Preston Pengra Briggs ,  Ron Diamant ,  Robert Geva

IPC: G06F8/41 ,  G06F12/06 ,  G06F9/30

CPC classification number: G06F8/41 ,  G06F8/441 ,  G06F9/30123 ,  G06F12/0646 ,  G06F2212/1024

Abstract: A compiler-implemented technique for performing a storage allocation is described. Computer code to be converted into machine instructions for execution on an integrated circuit device is received. The integrated circuit device includes a memory having a set of memory locations. Based on the computer code, a set of values that are to be stored on the integrated circuit device are determined. An interference graph that includes the set of values and a set of interferences is constructed. While traversing the interference graph, a set of memory location assignments are generated by assigning the set of values to the set of memory locations in accordance with one or more color selection schemes.