公开(公告)号：US09485129B1

公开(公告)日：2016-11-01

申请号：US14325184

申请日：2014-07-07

Applicant: Altera Corporation

Inventor： Benjamin Thomas Cope ,  Volker Mauer ,  Shahin Gheitanchi ,  Nima Safari

IPC: H04L27/26

CPC classification number: H04L27/2623

Abstract: Integrated circuits with wireless communications circuitry having peak cancelation circuitry operable to perform crest factor reduction is provided. The peak cancelation circuitry may receive at least first and second carrier waveforms and may include at least a first canceling pulse generator (CPG), a second CPG, a first peak detector for performing peak detection on the first waveform, a second peak detector for performing peak detection on the second waveform, a third peak detector for performing peak detection on a combined waveform of the first and second waveforms, and a pulse allocator that receives clipping information from the three peak detectors and that controls the amount of peak cancelation that is being performed by the two CPGs. The allocator may determine whether the combined waveform contains any peaks. In response to determining that the combined waveform does not contain any peaks, the CPGs may be configured in bypass mode.

Abstract translation: 提供具有无线通信电路的集成电路，其具有可操作以执行波峰因数降低的峰值消除电路。 峰值消除电路可以接收至少第一和第二载波波形，并且可以包括至少第一抵消脉冲发生器（CPG），第二CPG，用于在第一波形上执行峰值检测的第一峰值检测器，用于执行 在第二波形上的峰值检测，用于对第一和第二波形的组合波形执行峰值检测的第三峰值检测器，以及从三个峰值检测器接收限幅信息并且控制正在被去除的峰值消除量的脉冲分配器 由两个CPG执行。 分配器可以确定组合波形是否包含任何峰值。 响应于确定组合波形不包含任何峰值，CPG可以被配置为旁路模式。

公开(公告)号：US09000802B2

公开(公告)日：2015-04-07

申请号：US14153625

申请日：2014-01-13

Applicant: Altera Corporation

Inventor： Michael Fitton ,  Kulwinder Dhanoa ,  Benjamin Thomas Cope ,  Kellie Marks ,  Lei Xu

IPC: H03K19/0175

CPC classification number: H03K19/017581 ,  G06F13/385

Abstract: Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.

Abstract translation: 公开了用于在集成设备上实现的硬逻辑元件和软逻辑元件之间的接口的系统和方法。 特别地，提供了包括硬逻辑和软逻辑之间的互连的可配置接口，其使信号能够在硬逻辑块和软逻辑模块的输入和输出之间选择性地路由。 互连允许绕过某些硬逻辑块以有利于软逻辑功能。 此外，互连允许软逻辑来增加硬逻辑块的处理，例如通过向硬逻辑块提供附加信号。

公开(公告)号：US20140125379A1

公开(公告)日：2014-05-08

申请号：US14153625

申请日：2014-01-13

Applicant: Altera Corporation

Inventor： Michael Fitton ,  Kulwinder Dhanoa ,  Benjamin Thomas Cope ,  Kellie Marks ,  Lei Xu

IPC: H03K19/0175

CPC classification number: H03K19/017581 ,  G06F13/385

Abstract: Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.

Abstract translation: 公开了用于在集成设备上实现的硬逻辑元件和软逻辑元件之间的接口的系统和方法。 特别地，提供了包括硬逻辑和软逻辑之间的互连的可配置接口，其使信号能够在硬逻辑块和软逻辑模块的输入和输出之间选择性地路由。 互连允许绕过某些硬逻辑块以有利于软逻辑功能。 此外，互连允许软逻辑来增加硬逻辑块的处理，例如通过向硬逻辑块提供附加信号。