公开(公告)号：US4567380A

公开(公告)日：1986-01-28

申请号：US507496

申请日：1983-06-24

申请人： Yasushi Yasuda ,  Hiromu Enomoto ,  Yoshiki Shimauchi ,  Akinori Tahara

发明人： Yasushi Yasuda ,  Hiromu Enomoto ,  Yoshiki Shimauchi ,  Akinori Tahara

IPC分类号： H03K3/2893 ,  H03K3/295

CPC分类号： H03K3/2893

摘要： A level shift element is connected between a transistor (Tr.sub.5) which is used to determine a threshold level when the input voltage falls and a diode (D.sub.3) is connected between an input terminal and an output control transistor (Tr.sub.2) to discharge the base of the output control transistor. The level shift element comprises a diode connected in the forward direction or a resistor.

摘要翻译： 电平移动元件连接在用于在输入电压下降时确定阈值电平的晶体管（Tr5）和将二极管（D3）连接在输入端子和输出控制晶体管（Tr2）之间以将基极 输出控制晶体管。 电平移动元件包括在正向连接的二极管或电阻器。

公开(公告)号：US4888623A

公开(公告)日：1989-12-19

申请号：US256259

申请日：1988-10-12

申请人： Hiromu Enomoto ,  Yasushi Yasuda ,  Yoshiki Shimauchi ,  Akinori Tahara

发明人： Hiromu Enomoto ,  Yasushi Yasuda ,  Yoshiki Shimauchi ,  Akinori Tahara

IPC分类号： H01L21/74 ,  H01L21/822 ,  H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/47 ,  H01L29/866 ,  H01L29/872

CPC分类号： H01L21/74 ,  H01L21/743 ,  H01L27/0248

摘要： Electrostatical breakage of a semiconductor device, including an epitaxial layer and a buried layer thereunder, connected to an outer signal terminal, can be prevented by forming an impurity region in the epitaxial layer so as to form a PN junction between the buried layer and the impurity region. The impurity region is connected to a power source or ground.

摘要翻译： 可以通过在外延层中形成杂质区域来形成掩埋层和杂质之间的PN结，来防止连接到外部信号端子的包括其外部的外延层和掩埋层的半导体器件的静电破损 地区。 杂质区域连接到电源或接地。

公开(公告)号：US4774620A

公开(公告)日：1988-09-27

申请号：US98768

申请日：1987-09-17

申请人： Hiromu Enomoto ,  Yasushi Yasuda ,  Masao Kumagai ,  Akinori Tahara

发明人： Hiromu Enomoto ,  Yasushi Yasuda ,  Masao Kumagai ,  Akinori Tahara

IPC分类号： H03K19/088 ,  H03K17/082 ,  H03K17/60 ,  H03K19/003 ,  H02H3/20

CPC分类号： H03K19/00307 ,  H03K17/0826

摘要： A logic circuit which reduces occurrence of breakdown of the pull-down transistor and pull-up transistor in the output stage when a high voltage is applied to the power supply line and ensures high voltage resistance. The logic circuit controls a pull-up transistor provided between a first power supply and an output terminal which turns ON and OFF in accordance with a collector voltage of a phase splitter transistor and controls the pull-down transistor provided between the second power supply and output terminal with an emitter voltage. Breakdown of the pull-down and pull-up transistors can be reduced and a high voltage resistance ensured by providing a protection circuit which discharges the base of the pull-down transistor and turns OFF the pull-down transistor by detecting when a voltage difference between the first power supply and the second power supply exceeds a specified value.

摘要翻译： 一种逻辑电路，当向电源线施加高电压并且确保高电压电阻时，减小输出级中的下拉晶体管和上拉晶体管的击穿的发生。 所述逻辑电路控制设置在第一电源和输出端之间的上拉晶体管，所述上拉晶体管根据分相晶体管的集电极电压而导通和截止，并控制所述第二电源和输出端之间提供的下拉晶体管 端子具有发射极电压。 可以减小下拉和上拉晶体管的故障，并通过提供一个保护电路来确保高电压电阻，该保护电路对下拉晶体管的基极进行放电，并通过检测下拉晶体管的电压差 第一电源和第二电源超过规定值。

公开(公告)号：US4703202A

公开(公告)日：1987-10-27

申请号：US700413

申请日：1985-02-11

申请人： Hiromu Enomoto ,  Yasushi Yasuda ,  Akinori Tahara ,  Masao Kumagai

发明人： Hiromu Enomoto ,  Yasushi Yasuda ,  Akinori Tahara ,  Masao Kumagai

IPC分类号： G06F13/14 ,  G06F7/00 ,  H03K3/286 ,  H03K3/356 ,  H03K5/04 ,  H03K5/151 ,  H03K19/003 ,  H03K19/013 ,  H03K19/088

CPC分类号： H03K19/00307 ,  H03K19/00353 ,  H03K19/013 ,  H03K5/151

摘要： A gate circuit used for controlling an interface circuit in a microcomputer system, including a first-stage gate circuit, a second-stage gate circuit, and a control device connected between the first-stage gate circuit and the second-stage gate circuit. The first-stage gate circuit outputs an inverted strobe signal to the interface circuit, and the second-stage gate circuit outputs a non-inverted strobe signal to the interface circuit. Although there is a time lag in the changeover timing of these strobe signals, this time lag is reduced by connected the diode between the first-stage gate circuit and the second-stage gate circuit.

摘要翻译： 一种用于控制微机系统中的接口电路的门电路，包括连接在第一级门电路和第二级门电路之间的第一级门电路，二级门电路和控制装置。 第一级门电路向接口电路输出反相选通信号，第二级门电路向接口电路输出非反相选通信号。 尽管这些选通信号的转换定时存在时间滞后，但是通过连接第一级门电路和第二级门电路之间的二极管来减小该时滞。

公开(公告)号：US4680600A

公开(公告)日：1987-07-14

申请号：US921811

申请日：1986-10-21

申请人： Akinori Tahara ,  Hiromu Enomoto ,  Yasushi Yasuda

发明人： Akinori Tahara ,  Hiromu Enomoto ,  Yasushi Yasuda

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L27/02 ,  H01L29/861 ,  H03K19/003 ,  H01L29/56 ,  H01L29/90

CPC分类号： H01L27/0248 ,  H03K19/00307

摘要： A semiconductor device such as a TTL-type integrated circuit device which has an input protection circuit for each inner circuit, e.g., each TT logic gate. The input protection circuit is formed on a semiconductor substrate of a first conductivity type, and includes a first impurity region having a second conductivity type connected to an external terminal and an island-shape formed on the semiconductor substrate surrounded by an isolation region having the first conductivity type. The device also includes a clamp diode formed on an electrode layer contacting with the first impurity region. The device further includes a PN junction type protection diode formed on a second impurity region having the first conductivity type; the protection diode crosses the first impurity region between the clamp diode and a portion of the first impurity region connected to the external terminal and reaches the isolation region. The reverse withstand voltage of the PN junction type protection diode is smaller than that of the clamp diode, thereby preventing excessive reverse current flow and avoiding permanent destruction of the clamp diode.

摘要翻译： 诸如TTL型集成电路器件的半导体器件，其具有用于每个内部电路的输入保护电路，例如每个TT逻辑门。 输入保护电路形成在第一导电类型的半导体衬底上，并且包括具有连接到外部端子的第二导电类型的第一杂质区域和在由具有第一导电类型的隔离区域包围的半导体衬底上形成的岛状 导电类型。 该器件还包括形成在与第一杂质区接触的电极层上的钳位二极管。 该器件还包括形成在具有第一导电类型的第二杂质区上的PN结型保护二极管; 保护二极管穿过钳位二极管与连接到外部端子的第一杂质区域的一部分之间的第一杂质区域并到达隔离区域。 PN结型保护二极管的反向耐压小于钳位二极管的反向耐压，从而防止过大的反向电流流动，并避免钳位二极管的永久性破坏。

公开(公告)号：US5500542A

公开(公告)日：1996-03-19

申请号：US194988

申请日：1994-02-14

申请人： Takashi Iida ,  Satoru Sumi ,  Hiroshi Shimizu ,  Akinori Tahara ,  Isao Amano ,  Tetsuya Nakajima

发明人： Takashi Iida ,  Satoru Sumi ,  Hiroshi Shimizu ,  Akinori Tahara ,  Isao Amano ,  Tetsuya Nakajima

IPC分类号： H01L21/82 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118 ,  H01L27/10 ,  H01L23/62

CPC分类号： H01L27/0255 ,  H01L27/11803 ,  H01L2924/0002

摘要： Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.

公开(公告)号：US5672895A

公开(公告)日：1997-09-30

申请号：US575030

申请日：1995-12-19

申请人： Takashi Iida ,  Satoru Sumi ,  Hiroshi Shimizu ,  Akinori Tahara ,  Isao Amano ,  Tetsuya Nakajima

发明人： Takashi Iida ,  Satoru Sumi ,  Hiroshi Shimizu ,  Akinori Tahara ,  Isao Amano ,  Tetsuya Nakajima

IPC分类号： H01L21/82 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118 ,  H01L27/01 ,  H01L23/62 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L27/0255 ,  H01L27/11803 ,  H01L2924/0002

摘要： Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.

摘要翻译： 二极管行以与单元行的排列方向相同的方向以间隔L布置。 每个二极管行具有一排pn结，每一个pn结形成在衬底上并且沿垂直于互连轨道的轨道布置。 单元之间的互连将MOS晶体管的栅极自动连接到二极管，而不需要考虑哪个栅极应连接到二极管。 在制造半导体集成电路的过程中，MOS晶体管的栅极和二极管之间的布线长度小于防止栅极氧化物的静电击穿的上限值。 每个pn结可以形成在必要的输入信号线，必要的接地线，MOS晶体管的漏极的底部或者在宏单元之外的电源线下。

公开(公告)号：US6002155A

公开(公告)日：1999-12-14

申请号：US874980

申请日：1997-06-13

申请人： Akinori Tahara ,  Isao Amano

发明人： Akinori Tahara ,  Isao Amano

IPC分类号： H01L27/02 ,  H01L27/118 ,  H01L23/62

CPC分类号： H01L27/11803 ,  H01L27/0255 ,  H01L2924/0002

摘要： Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.

摘要翻译： 二极管行以与单元行的排列方向相同的方向以间隔L布置。 每个二极管行具有一排pn结，每一个pn结形成在衬底上并且沿垂直于互连轨道的轨道布置。 电池之间的互连自动将MOS晶体管的栅极连接到二极管，而不需要考虑哪个栅极应连接到二极管。 在制造半导体集成电路的过程中，MOS晶体管的栅极和二极管之间的布线长度小于防止栅极氧化物的静电击穿的上限值。 每个pn结可以形成在必要的输入信号线，必要的接地线，MOS晶体管的漏极的底部或者在宏单元之外的电源线下。

公开(公告)号：US4810908A

公开(公告)日：1989-03-07

申请号：US125648

申请日：1987-11-25

申请人： Hirokazu Suzuki ,  Akinori Tahara ,  Shinji Saito

发明人： Hirokazu Suzuki ,  Akinori Tahara ,  Shinji Saito

IPC分类号： H03K19/086 ,  H03K5/02 ,  H03K19/00 ,  H03K19/018 ,  H03K19/21

CPC分类号： H03K5/02 ,  H03K19/212

摘要： A semiconductor logic circuit comprises a clock driver circuit and a clocked circuit which carries out a clocked operation responsive to an output of the clock driver circuit, where an output logic amplitude of the clock driver circuit is set to a value which is greater than an internal logic amplitude of the clocked circuit and is less than or equal to four times the internal logic amplitude of the clocked circuit.

摘要翻译： 半导体逻辑电路包括时钟驱动器电路和时钟电路，其根据时钟驱动器电路的输出执行时钟操作，其中时钟驱动器电路的输出逻辑幅度被设置为大于内部 时钟电路的逻辑幅度小于或等于时钟电路的内部逻辑幅度的四倍。