公开(公告)号：US11605597B2

公开(公告)日：2023-03-14

申请号：US16852259

申请日：2020-04-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan Fang ,  Chun-Jun Zhuang

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/18 ,  H01L27/148

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.

公开(公告)号：US10886223B2

公开(公告)日：2021-01-05

申请号：US16430365

申请日：2019-06-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Jun Zhuang ,  Hsu-Nan Fang

IPC: H01L21/56 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a redistribution layer (RDL) structure, a first die, a molding compound and an interconnect structure. The first die is disposed on the RDL structure. The molding compound is disposed on the RDL structure. The interconnect structure electrically connects the first die to the RDL structure.

公开(公告)号：US12165982B2

公开(公告)日：2024-12-10

申请号：US17879677

申请日：2022-08-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan Fang ,  Chun-Jun Zhuang

IPC: H01L23/538 ,  H01L21/304 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31

Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.

公开(公告)号：US12142576B2

公开(公告)日：2024-11-12

申请号：US18121569

申请日：2023-03-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan Fang ,  Chun-Jun Zhuang

IPC: H01L23/544 ,  H01L21/56 ,  H01L23/00 ,  H01L23/18 ,  H01L23/31 ,  H01L27/148

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.

公开(公告)号：US11257788B2

公开(公告)日：2022-02-22

申请号：US16581009

申请日：2019-09-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan Fang ,  Chun-Jun Zhuang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L21/78 ,  H01L21/56

Abstract: A semiconductor device package includes a first electronic component, a plurality of first conductive traces, a second electronic component, a plurality of second conductive traces and a plurality of first conductive structures. The first electronic component has a first active surface. The first conductive traces are disposed on and electrically connected to the first active surface. The second electronic component is stacked on the first electronic component. The second electronic component has an inactive surface facing the first active surface, a second active surface opposite the inactive surface, and at least one lateral surface connecting the second active surface and the inactive surface. The second conductive traces are electrically connected to the second active surface, and extending from the second active surface to the lateral surface. The first conductive structures are electrically connecting the second conductive traces to the first conductive traces, respectively.

公开(公告)号：US11211319B2

公开(公告)日：2021-12-28

申请号：US16691296

申请日：2019-11-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan Fang ,  Chun-Jun Zhuang ,  Chen Yuan Weng

IPC: H01L23/498 ,  H01L23/528 ,  H01L23/544

Abstract: A device structure includes a first electronic structure and a plurality of first electric contacts. The first electronic structure has a surface and a center. The first electric contacts are exposed from the surface. The first electric contacts are spaced by a pitch that increases with increasing distance from the center.

公开(公告)号：US11139252B2

公开(公告)日：2021-10-05

申请号：US16802479

申请日：2020-02-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan Fang ,  Chun-Jun Zhuang ,  Yung I. Yeh

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.

公开(公告)号：US20190109117A1

公开(公告)日：2019-04-11

申请号：US16152270

申请日：2018-10-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan Fang ,  Chun-Jun Zhuang ,  Yung I. Yeh ,  Ming-Chiang Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor device package includes a first redistribution layer (RDL), a first die, a second die, a second RDL and an encapsulant. The first die is disposed on the first RDL and is electrically connected to the first RDL. The first die has a first electrical contact. The second die is disposed on the first RDL and is electrically connected to the first RDL. The second die has a first electrical contact. The second RDL is surrounded by the first RDL. The second RDL has a first electrical contact electrically connected to the first electrical contact of the first die and a second electrical contact electrically connected to the first electrical contact of the second die. A size of the first electrical contact of the second RDL is greater than a size of the second electrical contact of the second RDL.

公开(公告)号：US09911709B1

公开(公告)日：2018-03-06

申请号：US15335351

申请日：2016-10-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Jun Zhuang ,  Wei-Hang Tai ,  Pin-Ha Chuang

IPC: H01L23/00 ,  H01L23/24 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/16 ,  H01L23/24 ,  H01L23/295 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1403 ,  H01L2224/14517 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17155 ,  H01L2224/17179 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor device includes a first semiconductor die, a second semiconductor die and a plurality of supporting structures. The first semiconductor die includes a plurality of first bumps disposed adjacent to a first active surface thereof. The second semiconductor die includes a plurality of second bumps disposed adjacent to a second active surface thereof. The second bumps are bonded to the first bumps. The supporting structures are disposed between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die. The supporting structures are electrically isolated and are disposed adjacent to a peripheral region of the second active surface of the second semiconductor die.

公开(公告)号：US10797022B2

公开(公告)日：2020-10-06

申请号：US16152270

申请日：2018-10-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan Fang ,  Chun-Jun Zhuang ,  Yung I. Yeh ,  Ming-Chiang Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/367 ,  H01L21/48 ,  H01L23/498

Abstract: A semiconductor device package includes a first redistribution layer (RDL), a first die, a second die, a second RDL and an encapsulant. The first die is disposed on the first RDL and is electrically connected to the first RDL. The first die has a first electrical contact. The second die is disposed on the first RDL and is electrically connected to the first RDL. The second die has a first electrical contact. The second RDL is surrounded by the first RDL. The second RDL has a first electrical contact electrically connected to the first electrical contact of the first die and a second electrical contact electrically connected to the first electrical contact of the second die. A size of the first electrical contact of the second RDL is greater than a size of the second electrical contact of the second RDL.