DYNAMIC RANDOM-ACCESS MEMORY (DRAM) TRAINING ACCELERATION

    公开(公告)号:US20230132306A1

    公开(公告)日:2023-04-27

    申请号:US17506746

    申请日:2021-10-21

    Abstract: A method for performing read training of a memory channel includes writing a data pattern to a memory using a data bus having a predetermined number of bit lanes. An edge of a read data eye is determined individually for each bit lane by reading the data pattern over the data bus using a read bust cycle having a predetermined length, grouping data received on each bit lane over the read burst cycle to form a bit lane data group, and comparing the bit lane data group to corresponding expected data of the data pattern for each bit lane, logging a phase of each bit lane on which said edge is found, and repeating the reading, grouping, comparing, and logging until the edge is found for all of the bit lanes.

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