公开(公告)号：US09459877B2

公开(公告)日：2016-10-04

申请号：US13723296

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Stephan Diestelhorst ,  Martin Pohlack ,  Michael Hohmuth ,  David Christie ,  Luke Yen

IPC: G06F9/38 ,  G06F9/52

CPC classification number: G06F9/3842 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/528

Abstract: An apparatus, computer readable medium, and method of performing nested speculative regions are presented. The method includes responding to entering a speculative region by storing link information to an abort handler and responding to a commit command by removing link information from the abort handler. The method may include storing link information to the abort handler associated with the speculative region. When the speculative region is nested, the method may include storing link information to an abort handler associated with a previous speculative region. Removing link information may include removing link information from the abort handler associated with the corresponding speculative region. The method may include restoring link information to the abort handler associated with a previous speculative region. Responding to an abort command may include running the abort handler associated with the aborted speculative region. The method may include running the abort handler of each previous speculative region.

Abstract translation: 提出了一种执行嵌套投机区域的装置，计算机可读介质和方法。 该方法包括通过将中止处理程序的链接信息存储到中止处理程序并通过从中止处理程序中移除链接信息来响应提交命令来响应输入推测区域。 该方法可以包括将链接信息存储到与推测区域相关联的中止处理程序。 当推测区域被嵌套时，该方法可以包括将链接信息存储到与先前的推测区域相关联的中止处理程序。 删除链接信息可以包括从与相应的推测区域相关联的中止处理程序中移除链接信息。 该方法可以包括将链接信息恢复到与先前的推测区域相关联的中止处理程序。 响应中止命令可能包括运行与中止的投机区域相关联的中止处理程序。 该方法可以包括运行每个先前的推测区域的中止处理程序。

公开(公告)号：US08543775B2

公开(公告)日：2013-09-24

申请号：US13714132

申请日：2012-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Jaewoong Chung ,  David S Christie ,  Michael Hohmuth ,  Stephan Diestelhorst ,  Martin Pohlack ,  Luke Yen

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857

Abstract: A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.

Abstract translation: 公开了用于实现在硬件事务存储器系统中推测读取数据的早期释放的方法和装置。 处理核心包括硬件事务存储器系统，其被配置为接收活动事务的读取集合中的一组单词的指定字的早期释放指示。 早期释放指示包括从读取集中移除指定单词的请求。 响应于早期释放请求，处理核心仅在确定在活动事务期间没有推测性地读取除了指定单词之外的组中的任何单词之后才从读取集合中移除单词组。

公开(公告)号：US20140380022A1

公开(公告)日：2014-12-25

申请号：US13922340

申请日：2013-06-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Kai Troester ,  Luke Yen

IPC: G06F9/30

CPC classification number: G06F9/3004 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838

Abstract: A processor employs a prediction table at a front end of its instruction pipeline, whereby the prediction table stores address register and offset information for store instructions; and stack offset information for stack access instructions. The stack offset information for a corresponding instruction indicates the location of the data accessed by the instruction at the processor stack relative to a base location. The processor uses pattern matching to identify predicted dependencies between load/store instructions and predicted dependencies between stack access instructions. A scheduler unit of the instruction pipeline uses the predicted dependencies to perform store-to-load forwarding or other operations that increase efficiency and reduce power consumption at the processing system.

Abstract translation: 处理器在其指令流水线的前端采用预测表，由此预测表存储用于存储指令的地址寄存器和偏移信息; 和堆栈访问指令的堆栈偏移信息。 用于相应指令的堆栈偏移信息指示由处理器堆栈处的指令相对于基本位置访问的数据的位置。 处理器使用模式匹配来识别加载/存储指令之间的预测依赖性以及堆栈访问指令之间的预测依赖性。 指令流水线的调度器单元使用预测的依赖性来执行存储到负载转发或提高处理系统的效率并降低功耗的其他操作。

公开(公告)号：US20140379986A1

公开(公告)日：2014-12-25

申请号：US13922296

申请日：2013-06-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Kai Troester ,  Luke Yen

IPC: G06F12/08

CPC classification number: G06F9/38 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/3838

Abstract: A processor employs a prediction table at a front end of its instruction pipeline, whereby the prediction table stores address register and offset information for store instructions; and stack offset information for stack access instructions. The stack offset information for a corresponding instruction indicates the entry of the stack accessed by the instruction stack relative to a base entry. The processor uses pattern matching to identify predicted dependencies between load/store instructions and predicted dependencies between stack access instructions. A scheduler unit of the instruction pipeline uses the predicted dependencies to perform store-to-load forwarding or other operations that increase efficiency and reduce power consumption at the processing system.

Abstract translation: 处理器在其指令流水线的前端采用预测表，由此预测表存储用于存储指令的地址寄存器和偏移信息; 和堆栈访问指令的堆栈偏移信息。 相应指令的堆栈偏移信息指示由指令栈相对于基本条目访问的堆栈的条目。 处理器使用模式匹配来识别加载/存储指令之间的预测依赖性以及堆栈访问指令之间的预测依赖性。 指令流水线的调度器单元使用预测的依赖性来执行存储到负载转发或提高处理系统的效率并降低功耗的其他操作。

公开(公告)号：US20140136822A1

公开(公告)日：2014-05-15

申请号：US13673244

申请日：2012-11-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： David N. Suggs ,  Luke Yen ,  Steven Beigelmacher

IPC: G06F9/38

CPC classification number: G06F9/381 ,  G06F9/30065 ,  G06F9/30145 ,  G06F9/325 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3814 ,  G06F9/3867

Abstract: In a normal, non-loop mode a uOp buffer receives and stores for dispatch the uOps generated by a decode stage based on a received instruction sequence. In response to detecting a loop in the instruction sequence, the uOp buffer is placed into a loop mode whereby, after the uOps associated with the loop have been stored at the uOp buffer, storage of further uOps at the buffer is suspended. To execute the loop, the uOp buffer repeatedly dispatches the uOps associated with the loop's instructions until the end condition of the loop is met and the uOp buffer exits the loop mode.

Abstract translation: 在正常的非循环模式中，uOp缓冲器接收并存储用于根据接收的指令序列调度由解码级产生的uOps。 响应于检测到指令序列中的循环，将uOp缓冲器置于循环模式，由此在与循环相关联的uOps已经存储在uOp缓冲器之后，暂停在缓冲器处的进一步的uOps的存储。 要执行循环，uOp缓冲区会重复调度与循环指令相关联的uOps，直到满足循环的结束条件，并且uOp缓冲区退出循环模式。

公开(公告)号：US09710276B2

公开(公告)日：2017-07-18

申请号：US13673244

申请日：2012-11-09

Applicant: Advanced Micro Devices, Inc.

Inventor： David N. Suggs ,  Luke Yen ,  Steven Beigelmacher

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F9/381 ,  G06F9/30065 ,  G06F9/30145 ,  G06F9/325 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3814 ,  G06F9/3867

Abstract: In a normal, non-loop mode a uOp buffer receives and stores for dispatch the uOps generated by a decode stage based on a received instruction sequence. In response to detecting a loop in the instruction sequence, the uOp buffer is placed into a loop mode whereby, after the uOps associated with the loop have been stored at the uOp buffer, storage of further uOps at the buffer is suspended. To execute the loop, the uOp buffer repeatedly dispatches the uOps associated with the loop's instructions until the end condition of the loop is met and the uOp buffer exits the loop mode.

公开(公告)号：US09367310B2

公开(公告)日：2016-06-14

申请号：US13922340

申请日：2013-06-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Kai Troester ,  Luke Yen

IPC: G06F9/44 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838

Abstract: A processor employs a prediction table at a front end of its instruction pipeline, whereby the prediction table stores address register and offset information for store instructions; and stack offset information for stack access instructions. The stack offset information for a corresponding instruction indicates the location of the data accessed by the instruction at the processor stack relative to a base location. The processor uses pattern matching to identify predicted dependencies between load/store instructions and predicted dependencies between stack access instructions. A scheduler unit of the instruction pipeline uses the predicted dependencies to perform store-to-load forwarding or other operations that increase efficiency and reduce power consumption at the processing system.

Abstract translation: 处理器在其指令流水线的前端采用预测表，由此预测表存储用于存储指令的地址寄存器和偏移信息; 和堆栈访问指令的堆栈偏移信息。 用于相应指令的堆栈偏移信息指示由处理器堆栈处的指令相对于基本位置访问的数据的位置。 处理器使用模式匹配来识别加载/存储指令之间的预测依赖性以及堆栈访问指令之间的预测依赖性。 指令流水线的调度器单元使用预测的依赖性来执行存储到负载转发或提高处理系统的效率并降低功耗的其他操作。

公开(公告)号：US20130103908A1

公开(公告)日：2013-04-25

申请号：US13714132

申请日：2012-12-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jaewoong Chung ,  David S. Christie ,  Michael Hohmuth ,  Stephan Diestelhorst ,  Martin Pohlack ,  Luke Yen

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3857

Abstract: A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.

Abstract translation: 公开了用于实现在硬件事务存储器系统中推测读取数据的早期释放的方法和装置。 处理核心包括硬件事务存储器系统，其被配置为接收活动事务的读取集合中的一组单词的指定字的早期释放指示。 早期释放指示包括从读取集中移除指定单词的请求。 响应于早期释放请求，处理核心仅在确定在活动事务期间没有推测性地读取除了指定单词之外的组中的任何单词之后才从读取集合中移除单词组。

公开(公告)号：US10956163B2

公开(公告)日：2021-03-23

申请号：US15845641

申请日：2017-12-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jaewoong Chung ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin Pohlack ,  Luke Yen

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/46

Abstract: A processing core of a plurality of processing cores is configured to execute a speculative region of code a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.

公开(公告)号：US09292292B2

公开(公告)日：2016-03-22

申请号：US13922296

申请日：2013-06-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Kai Troester ,  Luke Yen

IPC: G06F12/06 ,  G06F9/38

CPC classification number: G06F9/38 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/3838

Abstract: A processor employs a prediction table at a front end of its instruction pipeline, whereby the prediction table stores address register and offset information for store instructions; and stack offset information for stack access instructions. The stack offset information for a corresponding instruction indicates the entry of the stack accessed by the instruction stack relative to a base entry. The processor uses pattern matching to identify predicted dependencies between load/store instructions and predicted dependencies between stack access instructions. A scheduler unit of the instruction pipeline uses the predicted dependencies to perform store-to-load forwarding or other operations that increase efficiency and reduce power consumption at the processing system.

Abstract translation: 处理器在其指令流水线的前端采用预测表，由此预测表存储用于存储指令的地址寄存器和偏移信息; 和堆栈访问指令的堆栈偏移信息。 相应指令的堆栈偏移信息指示由指令栈相对于基本条目访问的堆栈的条目。 处理器使用模式匹配来识别加载/存储指令之间的预测依赖性以及堆栈访问指令之间的预测依赖性。 指令流水线的调度器单元使用预测的依赖性来执行存储到负载转发或提高处理系统的效率并降低功耗的其他操作。