公开(公告)号：US20160117179A1

公开(公告)日：2016-04-28

申请号：US14523037

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric Morton ,  Patrick Conway ,  Greggory Douglas Donley ,  Vydhyanathan Kalyanasundharam

IPC: G06F9/445 ,  G06F9/54

CPC classification number: G06F9/44505 ,  G06F12/0815 ,  G06F17/5045 ,  G06F2217/68 ,  Y02D10/13

Abstract: A command replacement module at a coherency manager of a processor receives commands to be communicated over the communication fabric. For each received command of a specified type, the command replacement module compares a data payload of the command to a stored set of data patterns and, in response to a match, replaces the command with a replacement command, wherein the replacement command implies the contents of the data payload. The replacement command is communicated to the original commands destination via the communication fabric. In response to receiving the replacement command, the destination reconstructs the original command, deriving the data payload from the replacement command.

Abstract translation: 处理器的一致性管理器处的命令替换模块接收要在通信结构上传送的命令。 对于每个接收到的指定类型的命令，命令替换模块将命令的数据有效载荷与存储的数据模式集进行比较，并且响应于匹配，用替换命令替换命令，其中替换命令意味着内容 的数据有效载荷。 替换命令通过通信结构传送到原始命令目的地。 响应于接收到替换命令，目的地重建原始命令，从替换命令导出数据有效载荷。

公开(公告)号：US20160117248A1

公开(公告)日：2016-04-28

申请号：US14523045

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric Morton ,  Patrick Conway ,  Elizabeth Morrow Cooper ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/08 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F12/0815 ,  G06F11/3037 ,  G06F11/3409 ,  G06F2212/604 ,  Y02D10/13

Abstract: A processor includes a set of processing modules, each of the processing modules including a cache and a coherency manager that keeps track of the memory addresses of data stored at the caches of other processing modules. In response to its local cache requesting access to a particular memory address or other triggering event, the coherency manager generates a coherency probe. In the event that the generated coherency probe is targeted to multiple processing modules, the coherency manager includes a set of multicast bits indicating the processing modules whose caches include copies of the data targeted by the multicast probe. A transport switch that connects the processing module to the fabric communicates the coherency probe only to subset of processing modules indicated by the multicast bits.

Abstract translation: 处理器包括一组处理模块，每个处理模块包括高速缓存和一致性管理器，其跟踪存储在其他处理模块的高速缓存处的数据的存储器地址。 响应于其本地缓存请求访问特定存储器地址或其他触发事件，相关性管理器生成一致性探测器。 在生成的一致性探测针对多个处理模块的情况下，相关性管理器包括指示处理模块的一组多播位，其高速缓存包括多播探测器所针对的数据的副本。 将处理模块连接到结构的传输交换机仅将一致性探测器传送到由多播位指示的处理模块的子集。

公开(公告)号：US09507715B2

公开(公告)日：2016-11-29

申请号：US14523045

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric Morton ,  Patrick Conway ,  Elizabeth Morrow Cooper ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/08 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F12/0815 ,  G06F11/3037 ,  G06F11/3409 ,  G06F2212/604 ,  Y02D10/13

Abstract: A processor includes a set of processing modules, each of the processing modules including a cache and a coherency manager that keeps track of the memory addresses of data stored at the caches of other processing modules. In response to its local cache requesting access to a particular memory address or other triggering event, the coherency manager generates a coherency probe. In the event that the generated coherency probe is targeted to multiple processing modules, the coherency manager includes a set of multicast bits indicating the processing modules whose caches include copies of the data targeted by the multicast probe. A transport switch that connects the processing module to the fabric communicates the coherency probe only to subset of processing modules indicated by the multicast bits.

Abstract translation: 处理器包括一组处理模块，每个处理模块包括高速缓存和一致性管理器，其跟踪存储在其他处理模块的高速缓存处的数据的存储器地址。 响应于其本地缓存请求访问特定存储器地址或其他触发事件，相关性管理器生成一致性探测器。 在生成的一致性探测针对多个处理模块的情况下，相关性管理器包括指示处理模块的一组多播位，其高速缓存包括多播探测器所针对的数据的副本。 将处理模块连接到结构的传输交换机仅将一致性探测器传送到由多播位指示的处理模块的子集。

公开(公告)号：US20150120976A1

公开(公告)日：2015-04-30

申请号：US14522137

申请日：2014-10-23

Applicant: Advanced Micro Devices, Inc.

Inventor： William L. Walker ,  Paul J. Moyer ,  Richard M. Born ,  Eric Morton ,  David Christie ,  Marius Evers ,  Scott T. Bingham

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/10

CPC classification number: G06F12/0808 ,  G06F9/467 ,  G06F9/526 ,  G06F12/1027 ,  G06F12/1054 ,  G06F2209/522 ,  G06F2212/621 ,  G06F2212/682 ,  G06F2212/683

Abstract: A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.

Abstract translation: 用于执行总线锁定和翻译后备缓冲器无效事务的方法和装置包括由锁定主机接收来自系统中的第一处理器的锁定请求。 锁定主机向系统中的所有处理器发送静默请求，并且在收到来自锁定主机的停顿请求后，所有处理器都停止发出任何新的事务并发出静默授权交易。 在从所有处理器接收到暂停许可的交易之后，锁定主机发出包含第一处理器的标识符的锁授予消息。 第一个处理器执行原子事务序列，并在原子事务序列完成时向锁主机发送第一个锁定释放消息。 当从第一处理器接收到第一锁定释放消息时，锁定主机向所有处理器发送第二锁定释放消息。

公开(公告)号：US09916243B2

公开(公告)日：2018-03-13

申请号：US14522137

申请日：2014-10-23

Applicant: Advanced Micro Devices, Inc.

Inventor： William L. Walker ,  Paul J. Moyer ,  Richard M. Born ,  Eric Morton ,  David Christie ,  Marius Evers ,  Scott T. Bingham

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/0808 ,  G06F12/1045 ,  G06F12/1027 ,  G06F9/52 ,  G06F13/38 ,  G06F12/10

CPC classification number: G06F12/0808 ,  G06F9/467 ,  G06F9/526 ,  G06F12/1027 ,  G06F12/1054 ,  G06F2209/522 ,  G06F2212/621 ,  G06F2212/682 ,  G06F2212/683

Abstract: A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.

公开(公告)号：US20160117247A1

公开(公告)日：2016-04-28

申请号：US14523024

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric Morton ,  Patrick Conway ,  Alan Dodson Smith ,  Greggory Douglas Donley ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/08 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F12/0815 ,  G06F2212/604 ,  Y02D10/13

Abstract: A processor accumulating coherency probe responses, thereby reducing the impact of coherency messages on the bandwidth of the processor's communication fabric. A probe response accumulator is connected to a processing module of the processor, the processing module having multiple processor cores and associated caches. In response to a coherency probe, the processing module generates a different coherency probe response for each of the caches. The probe response accumulator combines the different coherency probe responses into a single coherency probe response and communicates the single coherency response over the communication fabric.

Abstract translation: 处理器累积一致性探测响应，从而减少一致性消息对处理器通信结构的带宽的影响。 探测响应累加器连接到处理器的处理模块，处理模块具有多个处理器核心和相关联的高速缓存。 响应于一致性探测器，处理模块为每个高速缓存生成不同的一致性探测器响应。 探测响应累加器将不同的一致性探测器响应组合成单个一致性探测器响应，并在通信结构上传送单个一致性响应。