公开(公告)号：US09300548B2

公开(公告)日：2016-03-29

申请号：US13273415

申请日：2011-10-14

申请人： Abhaya Asthana ,  Marc S. Benowitz ,  Uma Chandrashekhar

发明人： Abhaya Asthana ,  Marc S. Benowitz ,  Uma Chandrashekhar

IPC分类号： G06F15/173 ,  H04L12/24 ,  G06F9/50

CPC分类号： H04L41/5006 ,  G06F9/50 ,  H04L41/5025 ,  H04L41/5096

摘要： A dynamic reliability and security capability is provided. The dynamic reliability and security capability may be configured to support use of a dynamic reliability profile (DRP) that specifies the reliability parameters of a customer both as function of time and as a function of the requirements of the application or service of the customer. The reliability parameters may specify reliability requirements and/or goals of the customer, thereby providing a time varying requirements/goals profile. The dynamic reliability and security capability may be configured to dynamically configure the cloud resources to provide the required reliability as specified by the DRP. The RSG capability may be configured to subsequently monitor and meter the behavior to assure that the specified reliability is in fact being delivered, which may include use of self-healing capabilities to provide service assurance.

摘要翻译： 提供动态的可靠性和安全性。 可以将动态可靠性和安全性能力配置为支持动态可靠性概况（DRP）的使用，该动态可靠性简档（DRP）指定客户的可靠性参数，作为时间的函数，并且作为客户的应用或服务的要求的函数。 可靠性参数可指定客户的可靠性要求和/或目标，从而提供时变要求/目标简档。 可以将动态可靠性和安全性功能配置为动态配置云资源，以提供DRP规定的所需可靠性。 RSG功能可以被配置为随后监视和计量行为，以确保实际上正在传递指定的可靠性，其可以包括使用自愈能力来提供服务保证。

公开(公告)号：US5590370A

公开(公告)日：1996-12-31

申请号：US558208

申请日：1995-11-16

申请人： Abhaya Asthana ,  Mark R. Cravatts ,  Paul Krzyzanowski

发明人： Abhaya Asthana ,  Mark R. Cravatts ,  Paul Krzyzanowski

IPC分类号： G06F13/16 ,  G06F13/00 ,  G06F15/78 ,  G06F15/82 ,  G06F12/00

CPC分类号： G06F15/7821

摘要： A memory system contains one or more active storage elements. Each active storage element includes a memory element and a processing element associated with the memory element. The memory element contains microcode for implementing a specific function. A first bus connects the processing element to a host processor. A second bus connects the processing element to a peripheral.

摘要翻译： 存储器系统包含一个或多个活动存储元件。 每个活动存储元件包括存储器元件和与存储器元件相关联的处理元件。 存储元件包含用于实现特定功能的微码。 第一总线将处理元件连接到主机处理器。 第二总线将处理元件连接到外围设备。

公开(公告)号：US5740384A

公开(公告)日：1998-04-14

申请号：US603022

申请日：1996-02-16

申请人： Abhaya Asthana ,  Venkatesh Krishnaswamy

发明人： Abhaya Asthana ,  Venkatesh Krishnaswamy

IPC分类号： H04M11/00 ,  G06F13/38 ,  G06F13/40 ,  G06F19/00 ,  H04M11/06 ,  G06F13/36 ,  G06F13/00

CPC分类号： G06F13/409 ,  G06F13/385

摘要： A multimedia system includes a plurality of components. Each component has a set of hardware resources which are used to perform basic functions. Each component further contains knowledge regarding the properties, limitations and behavior of the resources. A backplane receives each of the components. The backplane includes a plurality of programmable interfaces. Each interface interfaces with a different component. A control thread is associated with each component which manages the resources contained in the component. The combination of the backplane, control thread and component form a basic service which operates independently from other basic services created by the system.

摘要翻译： 多媒体系统包括多个组件。 每个组件都有一组用于执行基本功能的硬件资源。 每个组件还包含有关资源的属性，限制和行为的知识。 背板接收每个组件。 背板包括多个可编程接口。 每个接口与不同的组件接口。 控制线程与管理组件中包含的资源的每个组件相关联。 背板，控制线程和组件的组合形成了独立于系统创建的其他基本服务的基本服务。

公开(公告)号：US08774790B2

公开(公告)日：2014-07-08

申请号：US11354709

申请日：2006-02-15

申请人： Abhaya Asthana ,  Eric Bauer ,  Peter Bosch ,  Xuemei Zhang

发明人： Abhaya Asthana ,  Eric Bauer ,  Peter Bosch ,  Xuemei Zhang

IPC分类号： H04M3/00

CPC分类号： H04M3/12 ,  H04W24/02 ,  H04W24/04 ,  H04W88/08

摘要： The invention includes a method and apparatus for reconfiguring a first base station element to attempt to serve at least a portion of the plurality of wireless terminals served by a second base station element in response to detection of a failure condition at a second base station element that was serving the plurality of wireless terminals prior to the occurrence of the failure condition.

摘要翻译： 本发明包括一种方法和装置，用于重新配置第一基站单元，以便响应于在第二基站单元处的故障状况的检测而尝试服务由第二基站单元服务的多个无线终端的至少一部分， 在发生故障条件之前为多个无线终端服务。

公开(公告)号：US4057711A

公开(公告)日：1977-11-08

申请号：US667960

申请日：1976-03-17

申请人： Abhaya Asthana ,  George Hannauer

发明人： Abhaya Asthana ,  George Hannauer

IPC分类号： G06J1/00

CPC分类号： G06J1/00

摘要： An analog switching system having fan-out for switching a plurality of inputs coupled to analog signal sources with respect to a plurality of outputs coupled to analog signal destinations. A three stage switch matrix includes input, middle and output switch blocks with each block having a plurality of analog switch means and latching means. Any one input terminal of a switch block may be connected to any one or more of the output terminals of that block. A matrix controller coupled to each of the switch blocks addresses each switch block and actuates at least one of the latching means to provide a connection assignment for at least one of the analog switching means.

摘要翻译： 一种模拟切换系统，具有扇出，用于相对于耦合到模拟信号目的地的多个输出切换耦合到模拟信号源的多个输入。 三级开关矩阵包括输入，中间和输出开关块，每个块具有多个模拟开关装置和锁存装置。 开关块的任何一个输入端子可以连接到该块的任何一个或多个输出端子。 耦合到每个开关块的矩阵控制器解决每个开关块并致动锁存装置中的至少一个以提供至少一个模拟开关装置的连接分配。

公开(公告)号：US20070226546A1

公开(公告)日：2007-09-27

申请号：US11315772

申请日：2005-12-22

申请人： Abhaya Asthana ,  Eric Bauer ,  Xuemei Zhang

发明人： Abhaya Asthana ,  Eric Bauer ,  Xuemei Zhang

IPC分类号： G06F11/00

CPC分类号： G06F11/008 ,  G06F11/3688

摘要： The invention includes a method for determining a software reliability metric, including obtaining testing defect data, obtaining test case data, determining testing exposure time data using the test case data, and computing the software reliability metric using testing defect data and testing exposure time data. The defect data includes software defect records. The test case data includes test case execution time data. A testing results profile is determined using testing defect data and testing exposure time data. A software reliability model is selected according to the testing results profile. A testing defect rate and a number of residual defects are determined by using the software reliability model and the testing results profile. A testing software failure rate is determined using the testing defect rate and the number of residual defects. A field software availability metric is determined using the field software failure rate determined using the testing software failure rate.

摘要翻译： 本发明包括一种用于确定软件可靠性度量的方法，包括获得测试缺陷数据，获得测试用例数据，使用测试用例数据确定测试曝光时间数据，以及使用测试缺陷数据和测试曝光时间数据计算软件可靠性度量。 缺陷数据包括软件缺陷记录。 测试用例数据包括测试用例执行时间数据。 使用测试缺陷数据和测试曝光时间数据确定测试结果配置文件。 根据测试结果配置文件选择软件可靠性模型。 通过使用软件可靠性模型和测试结果曲线确定测试缺陷率和残留缺陷数量。 使用测试缺陷率和剩余缺陷数确定测试软件故障率。 使用使用测试软件故障率确定的现场软件故障率来确定现场软件可用性度量。

公开(公告)号：US20070190996A1

公开(公告)日：2007-08-16

申请号：US11354709

申请日：2006-02-15

申请人： Abhaya Asthana ,  Eric Bauer ,  Peter Bosch ,  Xuemei Zhang

发明人： Abhaya Asthana ,  Eric Bauer ,  Peter Bosch ,  Xuemei Zhang

IPC分类号： H04M3/00

CPC分类号： H04M3/12 ,  H04W24/02 ,  H04W24/04 ,  H04W88/08

摘要： The invention includes a method and apparatus for reconfiguring a first base station element to attempt to serve at least a portion of the plurality of wireless terminals served by a second base station element in response to detection of a failure condition at a second base station element that was serving the plurality of wireless terminals prior to the occurrence of the failure condition.

摘要翻译： 本发明包括一种方法和装置，用于重新配置第一基站单元，以便响应于在第二基站单元处的故障状况的检测而尝试服务由第二基站单元服务的多个无线终端的至少一部分， 在发生故障条件之前为多个无线终端服务。

公开(公告)号：US6029224A

公开(公告)日：2000-02-22

申请号：US477175

申请日：1995-06-07

申请人： Abhaya Asthana ,  Douglas E. Haggan ,  King Lien Tai

发明人： Abhaya Asthana ,  Douglas E. Haggan ,  King Lien Tai

IPC分类号： G06F12/06 ,  G06F12/08 ,  G06F12/10 ,  G06F13/16 ,  G06F13/368

CPC分类号： G06F12/1027 ,  G06F12/0607 ,  G06F12/08 ,  G06F13/1694

摘要： An apparatus is provided that improves memory storage and access speed by repackaging various types of memories, SRAM, DRAM, and Disk, into a single storage unit. Each unit contains a slice of all the various memories along with programmable logic to control the accessing of the memories. This unit appears to the central processing unit (CPU) of a computer system as an extremely large secondary cache. Independent management of each unit greatly reduces bus traffic to implement any particular address space. By using a plurality of these memory units, an extremely large amount of memory can be accessed by the CPU with the speed of accessing a cache system.

摘要翻译： 提供了一种通过将各种类型的存储器，SRAM，DRAM和Disk重新打包成单个存储单元来提高存储器存储和访问速度的装置。 每个单元包含所有各种存储器的切片以及可编程逻辑以控制存储器的访问。 该单元以计算机系统的中央处理单元（CPU）显示为极大的二级缓存。 每个单元的独立管理大大减少了总线流量以实现任何特定的地址空间。 通过使用多个这样的存储单元，CPU可以以高速访问高速缓存系统来访问极大量的存储器。

公开(公告)号：US5134711A

公开(公告)日：1992-07-28

申请号：US193987

申请日：1988-05-13

申请人： Abhaya Asthana ,  Jonathan A. Chandross ,  Hosagrahar V. Jagadish ,  Scott C. Knauer ,  Daniel Lin

发明人： Abhaya Asthana ,  Jonathan A. Chandross ,  Hosagrahar V. Jagadish ,  Scott C. Knauer ,  Daniel Lin

IPC分类号： G06F15/16 ,  G06F9/46 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F15/173 ,  G06F15/177 ,  G06F15/78

CPC分类号： G06F9/5016 ,  G06F15/17381 ,  G06F15/7821 ,  G06F9/3879 ,  G06F9/461

摘要： A programmable memory system that interfaces with a computer's control and data manipulation units, and is capable of performing the manipulation, bookkeeping, and checking that would normally be performed by the computer. The memory system comprises active structure modules that are interconnected in a network to form clusters. The clusters are interconnected to form an aggregate memory system. Each ASE contains a processor section and a conventional memory section.

公开(公告)号：US4061904A

公开(公告)日：1977-12-06

申请号：US663297

申请日：1976-03-03

申请人： George Hannauer ,  Abhaya Asthana

发明人： George Hannauer ,  Abhaya Asthana

IPC分类号： G06J1/00 ,  G06G7/28

CPC分类号： G06J1/00

摘要： A variable analog function generator which is independent of an external computer during the time that it generates at least one predetermined output function of at least one input variable. The output function is expressed in terms of hybrid variables each having an analog portion and a digital portion. The function generator has a first dedicated memory which is loaded during set up time with data related to breakpoints defining the input variable. A second dedicated memory is loaded during set up time with tables of values defining the digital portion. During function generation, the analog portions are generated in response to (1) the input variable and (2) the data related to the breakpoints which is accessed in parallel from the first dedicated memory. The output function is generated in response to (1) the analog portions and (2) the tables of values accessed from the second dedicated memory.

摘要翻译： 可变模拟函数发生器，其在产生至少一个输入变量的至少一个预定输出函数的时间内独立于外部计算机。 输出功能以混合变量表示，每个混合变量具有模拟部分和数字部分。 函数发生器具有第一专用存储器，其在设置时间期间与与定义输入变量的断点相关的数据加载。 在设置时间期间，第二专用存储器加载了定义数字部分的值表。 在功能生成期间，响应于（1）输入变量和（2）与从第一专用存储器并行访问的断点相关的数据产生模拟部分。 响应于（1）模拟部分和（2）从第二专用存储器访问的值表生成输出功能。