公开(公告)号：US20140267468A1

公开(公告)日：2014-09-18

申请号：US13928394

申请日：2013-06-27

Applicant: AU Optronics Corp.

Inventor： Chun-Chieh Lin ,  Ya-Ling Chen

IPC: G09G3/32 ,  G09G5/10

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2320/0233

Abstract: A pixel of a display panel includes a first transistor with a first end coupled to a data line, a control end coupled to a scan line; a second transistor with a first end coupled to a first voltage source, a control end coupled to a second end of the first transistor; a third transistor with a first end coupled to a second end of the second transistor, a control end for receiving a control signal; a light emitting unit with a first end coupled to the second end of the second transistor, a second end coupled to a second voltage source; a first capacitor with a first end coupled to the second end of the first transistor, a second end coupled to a second end of the third transistor; and a second capacitor coupled between the second end of the first capacitor and the second voltage source.

Abstract translation: 显示面板的像素包括具有耦合到数据线的第一端的第一晶体管，耦合到扫描线的控制端; 第二晶体管，其第一端耦合到第一电压源，控制端耦合到第一晶体管的第二端; 第三晶体管，其第一端耦合到第二晶体管的第二端;控制端，用于接收控制信号; 发光单元，其第一端耦合到第二晶体管的第二端，第二端耦合到第二电压源; 第一电容器，其第一端耦合到第一晶体管的第二端，第二端耦合到第三晶体管的第二端; 以及耦合在第一电容器的第二端和第二电压源之间的第二电容器。

公开(公告)号：US20160049107A1

公开(公告)日：2016-02-18

申请号：US14583597

申请日：2014-12-27

Applicant: AU Optronics Corp.

Inventor： Wei-Chu Hsu ,  Man-Wen Shih ,  Ya-Ling Chen ,  Chien-Ya Lee

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28

Abstract: A shift register includes a plurality of shift register circuits. Each of the shift register circuits includes a first switch, an input circuit, a pull-down circuit and a ripple reduction circuit. The first switch is used to output a scanning signal of the shift register circuit according to voltage levels of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a scanning signal of a previous shift register circuit. The pull-down circuit is used to pull down the voltage levels of the node and the scanning signal of the shift register circuit according to a scanning signal of a following shift register circuit. The ripple reduction circuit is used to suppress ripples on the voltage levels of the node and the scanning signal caused by the coupling effect of the clock signal.

Abstract translation: 移位寄存器包括多个移位寄存器电路。 每个移位寄存器电路包括第一开关，输入电路，下拉电路和纹波降低电路。 第一开关用于根据节点的电压电平和时钟信号输出移位寄存器电路的扫描信号。 输入电路用于根据先前的移位寄存器电路的扫描信号来上拉节点的电压电平。 下拉电路用于根据随后的移位寄存器电路的扫描信号来降低节点的电压电平和移位寄存器电路的扫描信号。 纹波降低电路用于抑制由于时钟信号的耦合效应引起的节点电压电平和扫描信号的波动。

公开(公告)号：US09177505B2

公开(公告)日：2015-11-03

申请号：US13928394

申请日：2013-06-27

Applicant: AU Optronics Corp.

Inventor： Chun-Chieh Lin ,  Ya-Ling Chen

IPC: G09G3/12 ,  G09G3/32

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2320/0233

Abstract: A pixel of a display panel includes a first transistor with a first end coupled to a data line, a control end coupled to a scan line; a second transistor with a first end coupled to a first voltage source, a control end coupled to a second end of the first transistor; a third transistor with a first end coupled to a second end of the second transistor, a control end for receiving a control signal; a light emitting unit with a first end coupled to the second end of the second transistor, a second end coupled to a second voltage source; a first capacitor with a first end coupled to the second end of the first transistor, a second end coupled to a second end of the third transistor; and a second capacitor coupled between the second end of the first capacitor and the second voltage source.

Abstract translation: 显示面板的像素包括具有耦合到数据线的第一端的第一晶体管，耦合到扫描线的控制端; 第二晶体管，其第一端耦合到第一电压源，控制端耦合到第一晶体管的第二端; 第三晶体管，其第一端耦合到第二晶体管的第二端;控制端，用于接收控制信号; 发光单元，其第一端耦合到第二晶体管的第二端，第二端耦合到第二电压源; 第一电容器，其第一端耦合到第一晶体管的第二端，第二端耦合到第三晶体管的第二端; 以及耦合在第一电容器的第二端和第二电压源之间的第二电容器。

公开(公告)号：US09576517B2

公开(公告)日：2017-02-21

申请号：US14583597

申请日：2014-12-27

Applicant: AU Optronics Corp.

Inventor： Wei-Chu Hsu ,  Man-Wen Shih ,  Ya-Ling Chen ,  Chien-Ya Lee

IPC: G11C19/00 ,  G09G3/20 ,  G11C19/28

CPC classification number: G09G3/20 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28

Abstract: A shift register includes a plurality of shift register circuits. Each of the shift register circuits includes a first switch, an input circuit, a pull-down circuit and a ripple reduction circuit. The first switch is used to output a scanning signal of the shift register circuit according to voltage levels of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a scanning signal of a previous shift register circuit. The pull-down circuit is used to pull down the voltage levels of the node and the scanning signal of the shift register circuit according to a scanning signal of a following shift register circuit. The ripple reduction circuit is used to suppress ripples on the voltage levels of the node and the scanning signal caused by the coupling effect of the clock signal.

Abstract translation: 移位寄存器包括多个移位寄存器电路。 每个移位寄存器电路包括第一开关，输入电路，下拉电路和纹波降低电路。 第一开关用于根据节点的电压电平和时钟信号输出移位寄存器电路的扫描信号。 输入电路用于根据先前的移位寄存器电路的扫描信号来上拉节点的电压电平。 下拉电路用于根据随后的移位寄存器电路的扫描信号来降低节点的电压电平和移位寄存器电路的扫描信号。 纹波降低电路用于抑制由于时钟信号的耦合效应引起的节点电压电平和扫描信号的波动。