公开(公告)号：US20160049107A1

公开(公告)日：2016-02-18

申请号：US14583597

申请日：2014-12-27

Applicant: AU Optronics Corp.

Inventor： Wei-Chu Hsu ,  Man-Wen Shih ,  Ya-Ling Chen ,  Chien-Ya Lee

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28

Abstract: A shift register includes a plurality of shift register circuits. Each of the shift register circuits includes a first switch, an input circuit, a pull-down circuit and a ripple reduction circuit. The first switch is used to output a scanning signal of the shift register circuit according to voltage levels of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a scanning signal of a previous shift register circuit. The pull-down circuit is used to pull down the voltage levels of the node and the scanning signal of the shift register circuit according to a scanning signal of a following shift register circuit. The ripple reduction circuit is used to suppress ripples on the voltage levels of the node and the scanning signal caused by the coupling effect of the clock signal.

Abstract translation: 移位寄存器包括多个移位寄存器电路。 每个移位寄存器电路包括第一开关，输入电路，下拉电路和纹波降低电路。 第一开关用于根据节点的电压电平和时钟信号输出移位寄存器电路的扫描信号。 输入电路用于根据先前的移位寄存器电路的扫描信号来上拉节点的电压电平。 下拉电路用于根据随后的移位寄存器电路的扫描信号来降低节点的电压电平和移位寄存器电路的扫描信号。 纹波降低电路用于抑制由于时钟信号的耦合效应引起的节点电压电平和扫描信号的波动。

公开(公告)号：US09576517B2

公开(公告)日：2017-02-21

申请号：US14583597

申请日：2014-12-27

Applicant: AU Optronics Corp.

Inventor： Wei-Chu Hsu ,  Man-Wen Shih ,  Ya-Ling Chen ,  Chien-Ya Lee

IPC: G11C19/00 ,  G09G3/20 ,  G11C19/28

CPC classification number: G09G3/20 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28

Abstract: A shift register includes a plurality of shift register circuits. Each of the shift register circuits includes a first switch, an input circuit, a pull-down circuit and a ripple reduction circuit. The first switch is used to output a scanning signal of the shift register circuit according to voltage levels of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a scanning signal of a previous shift register circuit. The pull-down circuit is used to pull down the voltage levels of the node and the scanning signal of the shift register circuit according to a scanning signal of a following shift register circuit. The ripple reduction circuit is used to suppress ripples on the voltage levels of the node and the scanning signal caused by the coupling effect of the clock signal.

Abstract translation: 移位寄存器包括多个移位寄存器电路。 每个移位寄存器电路包括第一开关，输入电路，下拉电路和纹波降低电路。 第一开关用于根据节点的电压电平和时钟信号输出移位寄存器电路的扫描信号。 输入电路用于根据先前的移位寄存器电路的扫描信号来上拉节点的电压电平。 下拉电路用于根据随后的移位寄存器电路的扫描信号来降低节点的电压电平和移位寄存器电路的扫描信号。 纹波降低电路用于抑制由于时钟信号的耦合效应引起的节点电压电平和扫描信号的波动。

公开(公告)号：US09349324B2

公开(公告)日：2016-05-24

申请号：US14444157

申请日：2014-07-28

Applicant: AU OPTRONICS CORP.

Inventor： Hua-Gang Chang ,  Man-Wen Shih ,  Ching-Kai Lo ,  Chien-Chung Huang

IPC: G09G3/32

CPC classification number: G09G3/3291 ,  G09G3/3233 ,  G09G3/3258 ,  G09G3/3266 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/0248 ,  G09G2310/061 ,  G09G2320/0233 ,  G09G2320/043

Abstract: A pixel circuit includes four transistors, two capacitors and a light emitting element. A gate of first transistor receives a scan signal and a source/drain thereof receives a display data. A terminal of first capacitor couples to another source/drain of first transistor. A gate and a source/drain of second transistor couple to another terminal of first capacitor; and another source/drain thereof receives a switch signal. A terminal of second capacitor receives a reset signal; and another terminal thereof couples to another terminal of first capacitor. A gate of third transistor couples to a terminal of first capacitor. A gate of fourth transistor receives an enable signal; a source/drain thereof couples to a first power supply voltage; and another source/drain thereof couples to one source/drain of third transistor. The anode and cathode of the light emitting element couple to one source/drain of third transistor and a second power supply voltage, respectively.

Abstract translation: 像素电路包括四个晶体管，两个电容器和发光元件。 第一晶体管的栅极接收扫描信号，其源极/漏极接收显示数据。 第一电容器的端子耦合到第一晶体管的另一源极/漏极。 第二晶体管的栅极和源极/漏极耦合到第一电容器的另一个端子; 并且其另一个源极/漏极接收开关信号。 第二电容器的端子接收复位信号; 并且另一个端子耦合到第一电容器的另一个端子。 第三晶体管的栅极耦合到第一电容器的端子。 第四晶体管的栅极接收使能信号; 其源/漏耦合到第一电源电压; 并且其另一个源极/漏极耦合到第三晶体管的一个源极/漏极。 发光元件的阳极和阴极分别耦合到第三晶体管的一个源极/漏极和第二电源电压。