公开(公告)号：US08900900B2

公开(公告)日：2014-12-02

申请号：US13772346

申请日：2013-02-21

Applicant: AU Optronics Corp.

Inventor： Ming-Yao Chen ,  Pei-Ming Chen

IPC: H01L33/48 ,  H01L33/08 ,  H01L21/77

CPC classification number: H01L27/1225 ,  H01L21/77 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288

Abstract: A manufacturing method of an array substrate includes the following steps. A substrate having pixel region and a peripheral region is provided. A plurality of pixel structures are formed in the pixel region, wherein at least one of the pixel structures is formed by the following steps. A gate electrode, a gate insulating layer, and a source electrode and a drain electrode are formed. A patterned semiconductor layer including a first semiconductor pattern and a second semiconductor pattern is formed. The second semiconductor pattern covers a portion of the drain electrode. A first passivation layer is formed. The first passivation layer has a first opening exposing a portion of the second semiconductor pattern. A transparent conductive pattern is formed on the first passivation layer, and the transparent conductive pattern is electrically connected to the second semiconductor pattern through the first opening.

Abstract translation: 阵列基板的制造方法包括以下步骤。 提供具有像素区域和周边区域的基板。 在像素区域中形成多个像素结构，其中通过以下步骤形成至少一个像素结构。 形成栅电极，栅极绝缘层，以及源电极和漏电极。 形成包括第一半导体图案和第二半导体图案的图案化半导体层。 第二半导体图案覆盖漏电极的一部分。 形成第一钝化层。 第一钝化层具有暴露第二半导体图案的一部分的第一开口。 在第一钝化层上形成透明导电图案，透明导电图案通过第一开口与第二半导体图形电连接。

公开(公告)号：US09698180B2

公开(公告)日：2017-07-04

申请号：US15084458

申请日：2016-03-29

Applicant: AU Optronics Corp.

Inventor： Shin-Shueh Chen ,  Pei-Ming Chen

IPC: H01L21/00 ,  H01L27/144 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L31/18 ,  H01L31/02

CPC classification number: H01L27/1443 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/66765 ,  H01L29/66969 ,  H01L31/02005 ,  H01L31/1804 ,  H01L31/1864 ,  H01L31/1884 ,  H02S40/44

Abstract: An integration method of fabricating optical sensor device and thin film transistor device includes the follow steps. A substrate is provided, and a gate electrode and a bottom electrode are formed on the substrate. A first insulating layer is formed on the gate electrode and the bottom electrode, and the first insulating layer at least partially exposes the bottom electrode. An optical sensing pattern is formed on the bottom electrode. A patterned transparent semiconductor layer is formed on the first insulating layer, wherein the patterned transparent semiconductor layer includes a first transparent semiconductor pattern covering the gate electrode, and a second transparent semiconductor pattern covering the optical sensing pattern. A source electrode and a drain electrode are formed on the first transparent semiconductor pattern. A modification process including introducing at least one gas is performed on the second transparent semiconductor pattern to transfer the second transparent semiconductor pattern into a conductive transparent top electrode.

公开(公告)号：US20150048367A1

公开(公告)日：2015-02-19

申请号：US14526460

申请日：2014-10-28

Applicant: AU Optronics Corp.

Inventor： Ming-Yao Chen ,  Pei-Ming Chen

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L21/77 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288

Abstract: An array substrate includes a substrate and a plurality of pixel structures. At least one pixel structure includes a gate electrode, a gate insulating layer, a source electrode and a drain electrode, a patterned semiconductor layer, a first passivation layer, and a transparent conductive pattern disposed in a pixel region of the substrate. The patterned semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern. The first semiconductor pattern substantially corresponds to the gate electrode and covers a portion of the source electrode and a portion of the drain electrode. The second semiconductor pattern covers a portion of the drain electrode. The first passivation layer is disposed on the patterned semiconductor layer and has a first opening exposing a portion of the second semiconductor pattern. The transparent conductive pattern is disposed on the first passivation layer and electrically connected to the second semiconductor pattern through the first opening.

Abstract translation: 阵列基板包括基板和多个像素结构。 至少一个像素结构包括栅极，栅极绝缘层，源电极和漏电极，图案化半导体层，第一钝化层和布置在衬底的像素区域中的透明导电图案。 图案化半导体层包括第一半导体图案和第二半导体图案。 第一半导体图案基本上对应于栅电极并且覆盖源电极的一部分和漏电极的一部分。 第二半导体图案覆盖漏电极的一部分。 第一钝化层设置在图案化的半导体层上并且具有暴露第二半导体图案的一部分的第一开口。 透明导电图案设置在第一钝化层上，并通过第一开口与第二半导体图形电连接。

公开(公告)号：US20170069667A1

公开(公告)日：2017-03-09

申请号：US15084458

申请日：2016-03-29

Applicant: AU Optronics Corp.

Inventor： Shin-Shueh Chen ,  Pei-Ming Chen

IPC: H01L27/144 ,  H01L31/02 ,  H01L29/66 ,  H01L31/18 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L27/1443 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/66765 ,  H01L29/66969 ,  H01L31/02005 ,  H01L31/1804 ,  H01L31/1864 ,  H01L31/1884 ,  H02S40/44

Abstract: An integration method of fabricating optical sensor device and thin film transistor device includes the follow steps. A substrate is provided, and a gate electrode and a bottom electrode are formed on the substrate. A first insulating layer is formed on the gate electrode and the bottom electrode, and the first insulating layer at least partially exposes the bottom electrode. An optical sensing pattern is formed on the bottom electrode. A patterned transparent semiconductor layer is formed on the first insulating layer, wherein the patterned transparent semiconductor layer includes a first transparent semiconductor pattern covering the gate electrode, and a second transparent semiconductor pattern covering the optical sensing pattern. A source electrode and a drain electrode are formed on the first transparent semiconductor pattern. A modification process including introducing at least one gas is performed on the second transparent semiconductor pattern to transfer the second transparent semiconductor pattern into a conductive transparent top electrode.

Abstract translation: 制造光学传感器件和薄膜晶体管器件的集成方法包括以下步骤。 提供衬底，并且在衬底上形成栅电极和底电极。 在栅电极和底电极上形成第一绝缘层，并且第一绝缘层至少部分地露出底电极。 在底部电极上形成光学感测图案。 图案化的透明半导体层形成在第一绝缘层上，其中图案化的透明半导体层包括覆盖栅极的第一透明半导体图案和覆盖光学感测图案的第二透明半导体图案。 源电极和漏电极形成在第一透明半导体图案上。 在第二透明半导体图案上进行包括引入至少一种气体的改性处理，以将第二透明半导体图案转印到导电透明顶部电极中。

公开(公告)号：US09064749B2

公开(公告)日：2015-06-23

申请号：US14526460

申请日：2014-10-28

Applicant: AU Optronics Corp.

Inventor： Ming-Yao Chen ,  Pei-Ming Chen

IPC: H01L27/12 ,  H01L21/77

CPC classification number: H01L27/1225 ,  H01L21/77 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288

Abstract: An array substrate includes a substrate and a plurality of pixel structures. At least one pixel structure includes a gate electrode, a gate insulating layer, a source electrode and a drain electrode, a patterned semiconductor layer, a first passivation layer, and a transparent conductive pattern disposed in a pixel region of the substrate. The patterned semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern. The first semiconductor pattern substantially corresponds to the gate electrode and covers a portion of the source electrode and a portion of the drain electrode. The second semiconductor pattern covers a portion of the drain electrode. The first passivation layer is disposed on the patterned semiconductor layer and has a first opening exposing a portion of the second semiconductor pattern. The transparent conductive pattern is disposed on the first passivation layer and electrically connected to the second semiconductor pattern through the first opening.

Abstract translation: 阵列基板包括基板和多个像素结构。 至少一个像素结构包括栅极，栅极绝缘层，源电极和漏电极，图案化半导体层，第一钝化层和布置在衬底的像素区域中的透明导电图案。 图案化半导体层包括第一半导体图案和第二半导体图案。 第一半导体图案基本上对应于栅电极并且覆盖源电极的一部分和漏电极的一部分。 第二半导体图案覆盖漏电极的一部分。 第一钝化层设置在图案化的半导体层上并且具有暴露第二半导体图案的一部分的第一开口。 透明导电图案设置在第一钝化层上，并通过第一开口与第二半导体图形电连接。

公开(公告)号：US20140138714A1

公开(公告)日：2014-05-22

申请号：US13772346

申请日：2013-02-21

Applicant: AU OPTRONICS CORP.

Inventor： Ming-Yao Chen ,  Pei-Ming Chen

IPC: H01L33/48 ,  H01L33/08

CPC classification number: H01L27/1225 ,  H01L21/77 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288

Abstract: A manufacturing method of an array substrate includes the following steps. A substrate having pixel region and a peripheral region is provided. A plurality of pixel structures are formed in the pixel region, wherein at least one of the pixel structures is formed by the following steps. A gate electrode, a gate insulating layer, and a source electrode and a drain electrode are formed. A patterned semiconductor layer including a first semiconductor pattern and a second semiconductor pattern is formed. The second semiconductor pattern covers a portion of the drain electrode. A first passivation layer is formed. The first passivation layer has a first opening exposing a portion of the second semiconductor pattern. A transparent conductive pattern is formed on the first passivation layer, and the transparent conductive pattern is electrically connected to the second semiconductor pattern through the first opening.

Abstract translation: 阵列基板的制造方法包括以下步骤。 提供具有像素区域和周边区域的基板。 在像素区域中形成多个像素结构，其中通过以下步骤形成至少一个像素结构。 形成栅电极，栅极绝缘层，以及源电极和漏电极。 形成包括第一半导体图案和第二半导体图案的图案化半导体层。 第二半导体图案覆盖漏电极的一部分。 形成第一钝化层。 第一钝化层具有暴露第二半导体图案的一部分的第一开口。 在第一钝化层上形成透明导电图案，透明导电图案通过第一开口与第二半导体图形电连接。