公开(公告)号：US20150288364A1

公开(公告)日：2015-10-08

申请号：US14277918

申请日：2014-05-15

Applicant: AU OPTRONICS CORP.

Inventor： Wei-Li LIN ,  Che-Wei TUNG ,  Chia-Heng CHEN

IPC: H03K19/003

CPC classification number: H03K19/00384 ,  G09G2310/0286 ,  G11C19/28

Abstract: A shift register circuit includes a pull-down circuit, pull-down control circuit, a driving unit, a primary pull-down circuit and a gate driver circuit. The pull-down control circuit is electrically connected to the pull-down circuit and configured to provide an nth-stage pull-down control signal to the pull-down circuit. The a driving unit is electrically connected to the pull-down control circuit and configured to drive the pull-down control circuit. The primary pull-down circuit is electrically connected to the pull-down circuit. The gate driver circuit is electrically connected to the pull-down circuit and configured to output an nth-stage gate driving signal according to an nth-stage control signal. The driving unit is configured to receive a plurality of high-frequency clock signals and accordingly to pre-enable the pull-down control circuit, and n is a positive integer.

Abstract translation: 移位寄存器电路包括下拉电路，下拉控制电路，驱动单元，主下拉电路和栅极驱动器电路。 下拉控制电路电连接到下拉电路并且被配置为向下拉电路提供第n级下拉控制信号。 驱动单元电连接到下拉控制电路并且被配置为驱动下拉控制电路。 主下拉电路电连接到下拉电路。 栅极驱动器电路电连接到下拉电路并且被配置为根据第n级控制信号输出第n级栅极驱动信号。 驱动单元被配置为接收多个高频时钟信号，并相应地预先使能下拉控制电路，并且n是正整数。

公开(公告)号：US20170076821A1

公开(公告)日：2017-03-16

申请号：US15358939

申请日：2016-11-22

Applicant: AU OPTRONICS CORP.

Inventor： Wei-Li LIN ,  Che-Wei TUNG ,  Chia-Heng CHEN

IPC: G11C19/28 ,  G09G5/00

CPC classification number: G11C19/287 ,  G09G3/20 ,  G09G5/003 ,  G09G2310/0286 ,  G09G2310/06 ,  G09G2310/08 ,  G11C19/28

Abstract: A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number. A driving method of the aforementioned shift register group is also provided.

Abstract translation: 移位寄存器组包括多个串联耦合移位寄存器，每个移位寄存器被配置为提供输出信号。 多个移位寄存器的第一筛选寄存器的第三控制信号是由移位寄存器在第一移位寄存器之后N级提供的输出信号，第一筛选寄存器的第四控制信号是驱动节点处的电压 移位寄存器2N在第一移位寄存器之后分级，其中N是自然数。 还提供了上述移位寄存器组的驱动方法。

公开(公告)号：US20170186361A1

公开(公告)日：2017-06-29

申请号：US15375575

申请日：2016-12-12

Applicant: AU OPTRONICS CORP.

Inventor： Wei-Li LIN ,  Che-Wei Tung ,  Yan-Ting Chen

IPC: G09G3/20 ,  G11C19/18

CPC classification number: G09G3/2092 ,  G09G2300/0408 ,  G09G2300/0465 ,  G09G2300/0842 ,  G09G2310/0202 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28

Abstract: A shift register includes a control circuit, a switching circuit, a driving circuit, and a pull-down circuit. The control circuit is configured to output a control signal having a high level during a pull-up period and a voltage-regulating period respectively. The switching circuit is configured to provide a control voltage according to the control signal and a front stage signal outputted by a front x-stage shift register during the pull-up period. The driving circuit is configured to generate a driving signal according to the control voltage provided by the switching circuit, and output a home stage scan signal based on the driving signal. The pull-down circuit is configured to pull down a voltage level of the driving signal according to a scan signal outputted by a rear y-stage shift register during a pull-down period. The switching circuit is configured to regulate the driving signal and the home stage scan signal.

公开(公告)号：US20150255014A1

公开(公告)日：2015-09-10

申请号：US14324527

申请日：2014-07-07

Applicant: AU OPTRONICS CORP.

Inventor： Wei-Li LIN ,  Che-Wei TUNG ,  Chia-Heng CHEN

IPC: G09G3/20

CPC classification number: G11C19/287 ,  G09G3/20 ,  G09G5/003 ,  G09G2310/0286 ,  G09G2310/06 ,  G09G2310/08 ,  G11C19/28

Abstract: A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number. A driving method of the aforementioned shift register group is also provided.

Abstract translation: 移位寄存器组包括多个串联耦合移位寄存器，每个移位寄存器被配置为提供输出信号。 多个移位寄存器的第一筛选寄存器的第三控制信号是由移位寄存器在第一移位寄存器之后N级提供的输出信号，第一筛选寄存器的第四控制信号是驱动节点处的电压 移位寄存器2N在第一移位寄存器之后分级，其中N是自然数。 还提供了上述移位寄存器组的驱动方法。

公开(公告)号：US20140369457A1

公开(公告)日：2014-12-18

申请号：US14057317

申请日：2013-10-18

Applicant: AU OPTRONICS CORP.

Inventor： Wei-Li LIN ,  Chun-Huan CHANG ,  Che-Wei TUNG ,  Shu-Fang HOU

IPC: G11C19/28

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G2310/0286

Abstract: A shift register circuit includes a first pull-down control circuit, a first pull-down circuit electrically connecting to the first pull-down control circuit, a first inversed pulse signal coupling circuit outputting a first inversed pulse signal, a first pull-up circuit outputting a first gate control signal, and a first main pull-down circuit electrically connecting to the first pull-up circuit. The first pull-up circuit receives a first driving signal and a first pulse signal to output the first gate control signal. The first inversed pulse signal coupling circuit duly outputs the first inversed pulse signal to compensate a surge occurring in the first driving signal.

Abstract translation: 移位寄存器电路包括第一下拉控制电路，电连接到第一下拉控制电路的第一下拉电路，输出第一反相脉冲信号的第一反相脉冲信号耦合电路，第一上拉电路 输出第一栅极控制信号，以及电连接到第一上拉电路的第一主下拉电路。 第一上拉电路接收第一驱动信号和第一脉冲信号以输出第一门控制信号。 第一反相脉冲信号耦合电路适当地输出第一反相脉冲信号以补偿在第一驱动信号中发生的浪涌。