公开(公告)号：US20160062890A1

公开(公告)日：2016-03-03

申请号：US14640599

申请日：2015-03-06

Applicant: ARM LIMITED

Inventor： Sean James SALISBURY ,  Andrew David TUNE ,  Jamshed JALAL ,  Mark David WERKHEISER ,  Arthur LAUGHTON ,  George Robert Scott LLOYD ,  Peter Andrew RIOCREUX ,  Daniel SARA

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0815 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0673 ,  G06F2212/1021 ,  G06F2212/60

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

Abstract translation: 互连具有用于执行一致性控制操作的相关性控制电路和用于识别耦合到互连的哪些设备具有来自给定地址的缓存数据的窥探过滤器。 当在窥探过滤器中查找地址并丢失时，并且没有可用的备用侦听筛选器条目，则侦听筛选器将选择与受害者地址相对应的受害者条目，并发出无效的事务以使本地缓存的数据副本无效 由受害者确定。 用于执行数据访问事务的一致性检查操作的一致性控制电路被重新用于执行由窥探过滤器发出的无效事务的一致性控制操作。 这大大降低了窥探滤波器的电路复杂度。

公开(公告)号：US20190196990A1

公开(公告)日：2019-06-27

申请号：US15850296

申请日：2017-12-21

Applicant: Arm Limited

Inventor： Arthur Brian LAUGHTON ,  Sean James SALISBURY ,  Chiranjeev ACHARYA ,  Eduard VARDANYAN

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1678 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/4018 ,  G06F13/4022 ,  G06F13/4282 ,  G06F2213/0026 ,  G06F2213/4004

Abstract: An interconnect for providing data access between nodes of an integrated circuit, comprises a predetermined type of ingress port comprising routing circuitry responsive to a read-triggering request received from a requesting node to select from a selected egress port via which signals are to be routed to a destination node to control the destination node to return at least one read response dependent on data read from a target storage location. In response to the read-triggering request, the routing circuitry obtains a relative data width indication specifying whether read responses received at the selected egress port have a narrower data width than read responses to be provided to the requesting node by the predetermined type of ingress port, and controls allocation of resource for handling the read-triggering request or the at least one read response depending on the relative data width indication.

公开(公告)号：US20160055085A1

公开(公告)日：2016-02-25

申请号：US14467469

申请日：2014-08-25

Applicant: ARM LIMITED

Inventor： Sean James SALISBURY ,  Andrew David TUNE ,  Daniel SARA

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F2212/1016 ,  G06F2212/621

Abstract: An interconnect has transaction tracking circuitry for enforcing ordering of a set of data access transactions so that they are issued to slave devices in an order in which they are received from master devices. The transaction tracking circuitry is reused for also enforcing ordering of snoop transactions which are triggered by the set of data access transactions, for snooping master devices identified by a snoop filter as holding cache data for the target address of the transactions.

Abstract translation: 互连具有用于实施一组数据访问事务的排序的事务跟踪电路，使得它们以从主设备接收的顺序被发布到从设备。 交易跟踪电路被重新用于执行由一组数据访问事务触发的窥探事务的排序，用于窥探由窥探过滤器识别的主设备作为事务的目标地址的缓存数据。

公开(公告)号：US20150301961A1

公开(公告)日：2015-10-22

申请号：US14628331

申请日：2015-02-23

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Daniel SARA ,  Sean James SALISBURY ,  Arthur LAUGHTON ,  Peter Andrew RIOCREUX

IPC: G06F13/16

CPC classification number: G06F13/1626 ,  G06F13/1673

Abstract: A system-on-check integrated circuit 2 includes interconnect circuitry 4 connecting a plurality of transaction sources to a plurality of transaction destinations. The interconnect circuitry 4 includes a reorder buffer for buffering access transactions and hazard checking circuitry 46, 48, 50, 52 for performing hazard checks, such as point-of-serialisation checks and identifier reuse checks. Check suppression circuitry 62, 64, 66, 68 serves to suppress one or more hazard checks depending upon one or more state variables that themselves depend upon access transactions other than the access transaction for which the hazard checking is or is not to be suppressed. As an example, hazard checking may be suppressed if it is known that there are no other access transactions currently buffered within the reorder buffer 26 or alternatively no other access transactions from the same transaction source buffered within the reorder buffer 26.

Abstract translation: 系统对核心集成电路2包括将多个事务源连接到多个事务目的地的互连电路4。 互连电路4包括用于缓冲访问事务的重新排序缓冲器和用于执行诸如点序列化检查和标识符重用检查的危险检查的危险检查电路46,48,50,52。 检查抑制电路62,64,66,68用于根据一个或多个状态变量来抑制一个或多个危险检查，所述一个或多个状态变量本身依赖于非危险检查或不被抑制的访问事务以外的访问事务。 作为示例，如果知道当前没有其他访问事务在重新排序缓冲器26内缓冲，或者替代地没有来自在重排序缓冲器26内缓冲的相同事务源的其他访问事务，则可以抑制危险检查。

公开(公告)号：US20200250281A1

公开(公告)日：2020-08-06

申请号：US16267498

申请日：2019-02-05

Applicant: Arm Limited

Inventor： Sean James SALISBURY ,  Zheng XU ,  Arthur Brian LAUGHTON ,  Charles Filip BREJ

IPC: G06F17/50 ,  G06F9/30

Abstract: A method comprises generating, using a computer, an integrated circuit layout including a plurality of data handling nodes interconnected by routing circuitry defining data packet routes between the plurality of data handling nodes; for a transaction source node configured to generate data packets associated with a data handling translation between that transaction source node and a transaction target node and having one or more routing data fields controlling routing of the data packet, detecting, using the computer, a difference between a first routing controlled by the one or more routing data fields and a selected second routing provided by the integrated circuit layout; and providing, using the computer, one or more data mapping nodes in the integrated circuit layout to map an initial value of one or more of the routing data fields of a data packet generated by the transaction source node to a mapped data value, so that the mapped data value controls routing of the data packet using the selected second routing.

公开(公告)号：US20160350219A1

公开(公告)日：2016-12-01

申请号：US15133311

申请日：2016-04-20

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Sean James SALISBURY

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F12/0833 ,  G06F12/12 ,  G06F2212/1016

Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by a group of two or more cache memories in a coherent cache structure, which of the cache memories are caching those memory addresses, the directory being associative so that multiple memory addresses map to an associative set of more than one directory entry; and control logic responsive to a memory address to be newly cached, and configured to detect whether one or more of the set of directory entries mapped to that memory address is available for storage of an indication of which of the two or more cache memories are caching that memory address; the control logic being configured so that when all of the set of directory entries mapped to that memory address are occupied, the control logic is configured to select one of the set of directory entries as a directory entry to be overwritten and the corresponding cached information to be invalidated, the control logic being configured to select a directory entry to be overwritten, from the set of directory entries, in dependence upon which of the group of two or more cache memories is indicated by that directory entry, according to a likelihood of selection amongst the two or more cache memories.

Abstract translation: 高速缓存一致性控制器包括一个目录，指示对于由相干高速缓存结构中的一组两个或多个高速缓存存储器缓存的存储器地址，哪个高速缓存存储器缓存那些存储器地址，该目录是关联的，使得多个存储器地址映射到 多个目录条目的关联集合; 以及响应于要高速缓存的存储器地址的控制逻辑，并且被配置为检测映射到该存储器地址的该组目录条目中的一个或多个是否可用于存储两个或多个高速缓存存储器中的哪一个缓存的指示 那个内存地址; 所述控制逻辑被配置为使得当映射到所述存储器地址的所有所述目录条目集合被占用时，所述控制逻辑被配置为将所述一组目录条目中的一个选择为要被覆盖的目录条目，并且将相应的缓存信息 根据选择的可能性，控制逻辑被配置为根据目录条目集合来选择要覆盖的目录条目，这取决于该目录条目指示两个或多个高速缓冲存储器的组中的哪一个 在两个或多个缓存存储器中。

公开(公告)号：US20160103776A1

公开(公告)日：2016-04-14

申请号：US14874801

申请日：2015-10-05

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Arthur Brian LAUGHTON ,  Daniel Adam SARA ,  Sean James SALISBURY ,  Peter Andrew RIOCREUX

IPC: G06F13/364 ,  G06F15/78 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/4282

Abstract: Interconnect circuitry 10 for connecting transaction masters 4, 6, 8 to transaction slaves 12, 14 includes response modification circuitry 18. The response modification circuitry includes shortlist buffer circuitry 28 storing identification for modification target transaction responses. The response modification circuitry 18 uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry 18 then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master 4, 6, 8.

Abstract translation: 用于将交易主机4,6,8连接到交易从站12,14的互连电路10包括响应修改电路18.响应修改电路包括存储用于修改目标事务响应的标识的候选列表缓冲器电路28。 响应修改电路18使用该识别数据来识别传送中的事务响应流中的修改目标事务响应。 响应修改电路18然后用于形成被修改的事务响应，以代替对交易主机4,6,8的修改目标事务响应。

公开(公告)号：US20160350220A1

公开(公告)日：2016-12-01

申请号：US15133341

申请日：2016-04-20

Applicant: ARM LIMITED

Inventor： Sean James SALISBURY ,  Andrew David TUNE

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F12/0813 ,  G06F2212/1016

Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by one or more of a group of one or more cache memories connectable in a coherent cache structure, which of the cache memories are caching those memory addresses; and control circuitry configured to detect a directory entry relating to a memory address to be accessed so as to coordinate, amongst the cache memories, an access to a memory address by one of the cache memories or a coherent agent in instances when the directory entry indicates that another of the cache memories is caching that memory address; the control circuitry being responsive to status data indicating whether each cache memory in the group is currently subject to cache coherency control so as to take into account, in the detection of the directory entry relating to the memory address to be accessed, only those cache memories in the group which are currently subject to cache coherency control.

Abstract translation: 高速缓存一致性控制器包括一个目录，指示对于在一个连续高速缓存结构中可连接的一个或多个高速缓存存储器中的一个或多个存储器缓存的存储器地址，哪个高速缓存存储器缓存那些存储器地址; 以及控制电路，被配置为检测与要访问的存储器地址相关的目录条目，以便在所述高速缓冲存储器中，当所述目录条目指示的情况下，通过所述高速缓冲存储器之一或协调代理来协调对存储器地址的访问 另一个缓存存储器缓存该存储器地址; 控制电路响应状态数据，指示该组中的每个高速缓冲存储器当前是否经历高速缓存一致性控制，以便在检测与要访问的存储器地址相关的目录条目时仅考虑那些缓存存储器 在目前正在进行高速缓存一致性控制的组中。

公开(公告)号：US20160203094A1

公开(公告)日：2016-07-14

申请号：US14944340

申请日：2015-11-18

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Sean James SALISBURY

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  G06F12/08

CPC classification number: G06F13/4022 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/1673 ,  G06F13/4282 ,  G06F2212/1016 ,  G06F2212/622

Abstract: There is provided an interconnect for transferring requests between ports in which the ports include both source ports destination ports. The interconnect includes storage circuitry for storing the requests. Input circuitry receives the requests from the plurality of source ports, selects at least one selected source port from an allowed set of said plurality of source ports, and transfers a presented request from the at least one selected source port to the storage circuitry. Output circuitry causes a request in said storage circuitry to be output at one of said plurality of destination ports. Counter circuitry maintains counter values for a plurality of tracked ports from amongst said ports, each counter value indicating the number of requests in said storage circuitry associated with a corresponding tracked port that are waiting to be output by said output circuitry and filter circuitry determines whether or not a given source port is in said allowed set in dependence on said counter circuitry.

Abstract translation: 提供了用于在端口之间传送请求的互连，其中端口包括源端口目的端口。 互连包括用于存储请求的存储电路。 输入电路接收来自多个源端口的请求，从所述多个源端口的允许集合中选择至少一个选择的源端口，并将所呈现的请求从所述至少一个选择的源端口传送到存储电路。 输出电路使所述存储电路中的请求在所述多个目的地端口之一处输出。 计数器电路维护来自所述端口中的多个跟踪端口的计数器值，每个计数器值指示与正在等待由所述输出电路输出的相应跟踪端口相关联的所述存储电路中的请求数，并且滤波器电路确定是否 根据所述计数器电路，给定的源端口不在所述允许的集合中。

公开(公告)号：US20160062893A1

公开(公告)日：2016-03-03

申请号：US14822953

申请日：2015-08-11

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Sean James SALISBURY

IPC: G06F12/08

CPC classification number: G06F12/0833 ,  G06F12/0808 ,  G06F12/0831 ,  G06F2212/62 ,  G06F2212/621 ,  Y02D10/13

Abstract: An interconnect and method of managing a snoop filter within such an interconnect are provided. The interconnect is used to connect a plurality of devices, including a plurality of master devices where one or more of the master devices has an associated cache storage. The interconnect comprises coherency control circuitry to perform coherency control operations for data access transactions received by the interconnect from the master devices. In performing those operations, the coherency control circuitry has access to snoop filter circuitry that maintains address-dependent caching indication data, and is responsive to a data access transaction specifying a target address to produce snoop control data providing an indication of which master devices have cached data for the target address in their associated cache storage. The coherency control circuitry then responds to the snoop control data by issuing a snoop transaction to each master device indicated by the snoop control data, in order to cause a snoop operation to be performed in their associated cache storage in order to generate snoop response data. Analysis circuitry then determines from the snoop response data an update condition, and upon detection of the update condition triggers performance of an update operation within the snoop filter circuitry to update the address-dependent caching indication data. By subjecting the snoop response data to such an analysis, it is possible to identify situations where the caching indication data has become out of date, and update that caching indication data accordingly, this giving rise to significant performance benefits in the operation of the interconnect.

Abstract translation: 提供了在这种互连内管理窥探滤波器的互连和方法。 互连用于连接多个设备，包括多个主设备，其中一个或多个主设备具有相关联的高速缓存存储器。 互连包括一致性控制电路，用于对由主设备的互连接收的数据访问事务执行一致性控制操作。 在执行这些操作时，相关性控制电路可以访问保持地址相关的缓存指示数据的窥探滤波器电路，并且响应于指定目标地址的数据访问事务来产生窥探控制数据，提供哪些主设备已被缓存的指示 其相关缓存存储中的目标地址的数据。 相关性控制电路然后通过向窥探控制数据指示的每个主设备发出窥探事务来响应窥探控制数据，以便在其关联的高速缓存存储器中执行窥探操作，以便产生窥探响应数据。 分析电路然后从窥探响应数据确定更新条件，并且在检测到更新条件时，触发窥探过滤器电路内的更新操作的执行，以更新依赖于地址的高速缓存指示数据。 通过对窥探响应数据进行这种分析，可以识别高速缓存指示数据已经过时的情况，并相应地更新缓存指示数据，这在互连操作中产生显着的性能益处。