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公开(公告)号：US11127110B2
公开(公告)日：2021-09-21
申请号：US15446997
申请日：2017-03-01
Applicant: ARM Limited , APICAL LIMITED
Inventor： Ian Rudolf Bratt , Alexander Eugene Chalfin , Eric Kunze , Paul Stanley Hughes , Alex Kornienko , Damian Piotr Modrzyk , Metin Gokhan Ünal , Jonathan Adam Lawton
Abstract: A display controller 93 in a data processing system includes a timewarp module (transformation circuitry) 100 that is operable to perform timewarp processing of a rendered frame 92 generated by a graphics processor (GPU) 91 for provision to a display panel 94. The timewarp module (transformation circuitry) 100 operates to transform an input surface 92 read by the display controller 93 based on received view orientation data to provide an appropriately “timewarped” transformed version of the input surface as an output transformed surface for display on the display 94.
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公开(公告)号：US10540281B2
公开(公告)日：2020-01-21
申请号：US15407681
申请日：2017-01-17
Applicant: ARM Limited
Inventor： Paul Stanley Hughes , Michael Andrew Campbell
IPC: G06F12/00 , G06F12/0804 , G06F12/121 , G06F12/127 , G06F12/122 , G06F12/123 , G06F12/0888
Abstract: A cache to provide data caching in response to data access requests from at least one system device, and a method operating such a cache, are provided. Allocation control circuitry of the cache is responsive to a cache miss to allocate an entry of the multiple entries in the data caching storage circuitry in dependence on a cache allocation policy. Quality-of-service monitoring circuitry is responsive to a quality-of-service indication to modify the cache allocation policy with respect to allocation of the entry for the requested data item. The behaviour of the cache, in particular regarding allocation and eviction, can therefore be modified in order to seek to maintain a desired quality-of-service for the system in which the cache is found.
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公开(公告)号：US20180253868A1
公开(公告)日：2018-09-06
申请号：US15446997
申请日：2017-03-01
Applicant: ARM Limited , APICAL LIMITED
Inventor： Ian Rudolf Bratt , Alexander Eugene Chalfin , Eric Kunze , Paul Stanley Hughes , Alex Kornienko , Damian Piotr Modrzyk , Metin Gokhan Ünal , Jonathan Adam Lawton
CPC classification number: G06T1/60 , G06F3/012 , G06T3/0093 , G09G5/36 , G09G5/391 , G09G5/395 , G09G2340/0464 , G09G2354/00
Abstract: A display controller 93 in a data processing system includes a timewarp module (transformation circuitry) 100 that is operable to perform timewarp processing of a rendered frame 92 generated by a graphics processor (GPU) 91 for provision to a display panel 94. The timewarp module (transformation circuitry) 100 operates to transform an input surface 92 read by the display controller 93 based on received view orientation data to provide an appropriately “timewarped” transformed version of the input surface as an output transformed surface for display on the display 94.
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公开(公告)号：US11106513B2
公开(公告)日：2021-08-31
申请号：US16755269
申请日：2018-09-04
Applicant: ARM Limited
IPC: G06F9/44 , G06F9/54 , G06F9/30 , G06F12/02 , G06F12/0873
Abstract: A data processing system and method of data processing are provided. The system comprises first and second data processing agents and data storage shared coherently between the both data processing agents to store a message data structure to provide a message channel between them. A further data storage is accessible to both data processing agents to store message channel metadata, which provides message status information for the message channel. The message channel metadata is one of a plurality of message channel metadata types defined for a corresponding plurality of message channel types between the first and second data processing agents, and at least one of the first and second data processing agents is responsive to an initialization trigger to establish the message channel with a selected message channel type.
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