公开(公告)号：US20140374907A1

公开(公告)日：2014-12-25

申请号：US14305906

申请日：2014-06-16

Applicant: APPLIED MATERIALS, INC.

Inventor： Jick M. YU ,  Rong TAO

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76873 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and process are described that allow electroplating to fill sub-micron, high aspect ratio semiconductor substrate features using a non-copper/pre-electroplating layer on at least upper portions of side walls of the features, thereby providing reliable bottom up accumulation of the electroplating fill material in the feature. This apparatus and process eliminates feature filling material voids and enhances reliability of the electroplating in the diminishing size of features associated with future technology nodes of 22, 15, 11, and 8 nm. Modification of an upper portion of a metal seed layer allows for filling of the feature using electroplated fill material accumulating from the bottom of the feature up to reliability and predictability and substantially void-free.

Abstract translation: 描述了一种装置和方法，其允许电镀在特征的侧壁的至少上部上使用非铜/预电镀层填充亚微米，高纵横比的半导体衬底特征，由此提供可靠的自下而上的积累 电镀填充材料的特点。 该设备和工艺消除了特征填充材料的空隙，并增强了与22,15,11和8nm的未来技术节点相关联的特征尺寸减小的电镀的可靠性。 金属种子层的上部的修改允许使用从特征的底部累积的电镀填充材料到可靠性和可预测性以及基本上无空隙来填充特征。