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公开(公告)号：US11025406B2
公开(公告)日：2021-06-01
申请号：US16584012
申请日：2019-09-26
Applicant: Apple Inc.
Inventor： Michael F. Jean , Adam E. Kriegel , Brett D. George , Daniel C. Klingler , Girault W. Jones , Felipe Ferreri Tonello
Abstract: A system and method to mitigate the temporary loss of the input sampling clocks when receiving audio data over the ARC or eARC interface of HDMI are provided. A media device may substitute an externally generated clock derived from a local crystal oscillator of the media device for the missing input sampling clock. The external clock may be synchronized to the frequency of the input sampling clock. The media device may synchronize the external clock to the audio data when there is a loss of the input sampling clock. When the input sampling clock of the audio data reappears, the media device may switch back from the external clock to the input sampling clock. When transitioning between the input sampling clock and the external clock, the media device may insert zero padding into the audio data samples to mute any potential glitch in the sound from an audio playback device.
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公开(公告)号：US11886365B2
公开(公告)日：2024-01-30
申请号：US17475074
申请日：2021-09-14
Applicant: Apple Inc.
Inventor： Brett D. George , Rohit K. Gupta , Do Kyung Kim , Paul W. Glendenning
IPC: G06F13/28
CPC classification number: G06F13/28 , G06F2213/28
Abstract: Techniques for improving the handling of peripherals in a computer system, including through the use of a DMA control circuit that helps manage the flow of data between memory and the peripherals via an intermediate storage buffer. The DMA control circuit is configured to control timing of DMA transfers between sample buffers in the memory and the intermediate storage buffer. The DMA control circuit may output a priority value of the DMA control circuit for accesses to memory, where the priority value based on stored quality of service (QoS) information and current channel data buffer levels for different DMA channels. The DMA control circuit may separately arbitrate between multiple active transmit and receive channels. Still further, the DMA control circuit may store, for a given data transfer over a particular DMA channel, timestamp information indicative of completion of the DMA and peripheral-side operations.
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公开(公告)号：US20210098011A1
公开(公告)日：2021-04-01
申请号：US16584008
申请日：2019-09-26
Applicant: Apple Inc.
Inventor： Brett D. George , Adam E. Kriegel , Michael F. Jean , Daniel C. Klingler , Girault W. Jones , Felipe Ferreri Tonello
IPC: G10L19/16
Abstract: A system and method to process audio data received over the ARC or eARC interface of HDMI from audio sources are provided. A media device may receive compressed audio data in a number of data formats. The media device may convert between the audio formats provided by the audio sources and the audio formats supported by audio playback devices. The media device may inspect frames of audio data to determine if the frames are to be decoded. The frame may be decoded and subsequently encoded into the data formats supported by the audio playback devices. To reduce latency, the media device may enable a pass-through mode to bypass the decoding of the frames to allow the frames to be decoded at the audio playback devices. A bi-directional loopback application may route audio data received over the ARC or eARC interface from the audio sources to the audio playback devices.
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公开(公告)号：US20240143530A1
公开(公告)日：2024-05-02
申请号：US18404449
申请日：2024-01-04
Applicant: Apple Inc.
Inventor： Brett D. George , Rohit K. Gupta , Do Kyung Kim , Paul W. Glendenning
IPC: G06F13/28
CPC classification number: G06F13/28 , G06F2213/28
Abstract: Techniques for improving the handling of peripherals in a computer system, including through the use of a DMA control circuit that helps manage the flow of data between memory and the peripherals via an intermediate storage buffer. The DMA control circuit is configured to control timing of DMA transfers between sample buffers in the memory and the intermediate storage buffer. The DMA control circuit may output a priority value of the DMA control circuit for accesses to memory, where the priority value based on stored quality of service (QoS) information and current channel data buffer levels for different DMA channels. The DMA control circuit may separately arbitrate between multiple active transmit and receive channels. Still further, the DMA control circuit may store, for a given data transfer over a particular DMA channel, timestamp information indicative of completion of the DMA and peripheral-side operations.
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公开(公告)号：US11200303B2
公开(公告)日：2021-12-14
申请号：US16144922
申请日：2018-09-27
Applicant: Apple Inc.
Inventor： Gregory F. Hughes , Anthony J. Chivetta , Brett D. George , Josh P. de Cesare , Santo S. Sapienza , Ion Valentin Pistol
Abstract: Techniques are disclosed relating to providing audio prompts. In one embodiment, a computing device includes a display, an audio circuit coupled to a speaker, first and second processors, and memory. The memory has first program instructions executable by the first processor to provide, via a first operating system of the computing device, a visual prompt to the display to cause the display to present the visual prompt to a user and send, to the second processor, a request to provide an audio prompt corresponding to the visual prompt via the speaker to the user. The computing device also includes memory having second program instructions executable by the second processor to, in response to the request, provide, via a second operating system, an instruction to the audio circuit to play the audio prompt via the speaker.
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Patent Agency Ranking
公开(公告)号：US20210099278A1
公开(公告)日：2021-04-01
申请号：US16584012
申请日：2019-09-26
Applicant: Apple Inc.
Inventor： Michael F. Jean , Adam E. Kriegel , Brett D. George , Daniel C. Klingler , Girault W. Jones , Felipe Ferreri Tonello
Abstract: A system and method to mitigate the temporary loss of the input sampling clocks when receiving audio data over the ARC or eARC interface of HDMI are provided. A media device may substitute an externally generated clock derived from a local crystal oscillator of the media device for the missing input sampling clock. The external clock may be synchronized to the frequency of the input sampling clock. The media device may synchronize the external clock to the audio data when there is a loss of the input sampling clock. When the input sampling clock of the audio data reappears, the media device may switch back from the external clock to the input sampling clock. When transitioning between the input sampling clock and the external clock, the media device may insert zero padding into the audio data samples to mute any potential glitch in the sound from an audio playback device.
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公开(公告)号：US20130293558A1
公开(公告)日：2013-11-07
申请号：US13875215
申请日：2013-05-01
Applicant: APPLE INC.
Inventor： Brett D. George , Changki Min , David A. Leech , Matthew X. Mora , Neil D. Warren , Rajabali M. Koduri , Ronald N. Isaac
IPC: G06T1/20
CPC classification number: G06T1/20 , G10K2210/3042
Abstract: Methods and apparatus for processing media signals. In one embodiment, a data processing device processes fixed and variable rate data using a first and second processing unit. The processing comprises real-time processing of audio/video signals by a graphics processing unit (GPU) and/or central processing unit (CPU). The processing units process data efficiently by establishing one processor as always processing variable rate data, and using one or more schemes for determining processor will process fixed rate data. A shared memory enables the processors to communicate with one another in order to determine which will process the fixed rate data. In one scheme for determining which of the processors will process the fixed rate data the second processor need merely be unlocked. In another embodiment, the second processor must be unlocked and immediately available.
Abstract translation: 用于处理媒体信号的方法和装置。 在一个实施例中，数据处理设备使用第一和第二处理单元处理固定和可变速率数据。 该处理包括由图形处理单元（GPU）和/或中央处理单元（CPU）对音频/视频信号的实时处理。 处理单元通过一如既往处理可变速率数据建立一个处理器，并且使用一个或多个用于确定处理器的方案将处理固定速率数据来有效地处理数据。 共享存储器使处理器能够彼此通信，以便确定哪个处理固定速率数据。 在用于确定哪些处理器将处理固定速率数据的一种方案中，第二处理器仅需要解锁。 在另一个实施例中，第二处理器必须被解锁并立即可用。
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公开(公告)号：US11514921B2
公开(公告)日：2022-11-29
申请号：US16584008
申请日：2019-09-26
Applicant: Apple Inc.
Inventor： Brett D. George , Adam E. Kriegel , Michael F. Jean , Daniel C. Klingler , Girault W. Jones , Felipe Ferreri Tonello
IPC: G10L19/16
Abstract: A system and method to process audio data received over the ARC or eARC interface of HDMI from audio sources are provided. A media device may receive compressed audio data in a number of data formats. The media device may convert between the audio formats provided by the audio sources and the audio formats supported by audio playback devices. The media device may inspect frames of audio data to determine if the frames are to be decoded. The frame may be decoded and subsequently encoded into the data formats supported by the audio playback devices. To reduce latency, the media device may enable a pass-through mode to bypass the decoding of the frames to allow the frames to be decoded at the audio playback devices. A bi-directional loopback application may route audio data received over the ARC or eARC interface from the audio sources to the audio playback devices.
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公开(公告)号：US20220083486A1
公开(公告)日：2022-03-17
申请号：US17475074
申请日：2021-09-14
Applicant: Apple Inc.
Inventor： Brett D. George , Rohit K. Gupta , Do Kyung Kim , Paul W. Glendenning
IPC: G06F13/28
Abstract: Techniques for improving the handling of peripherals in a computer system, including through the use of a DMA control circuit that helps manage the flow of data between memory and the peripherals via an intermediate storage buffer. The DMA control circuit is configured to control timing of DMA transfers between sample buffers in the memory and the intermediate storage buffer. The DMA control circuit may output a priority value of the DMA control circuit for accesses to memory, where the priority value based on stored quality of service (QoS) information and current channel data buffer levels for different DMA channels. The DMA control circuit may separately arbitrate between multiple active transmit and receive channels. Still further, the DMA control circuit may store, for a given data transfer over a particular DMA channel, timestamp information indicative of completion of the DMA and peripheral-side operations.
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公开(公告)号：US20190180015A1
公开(公告)日：2019-06-13
申请号：US16144922
申请日：2018-09-27
Applicant: Apple Inc.
Inventor： Gregory F. Hughes , Anthony J. Chivetta , Brett D. George , Josh P. de Cesare , Santo S. Sapienza , Ion Valentin Pistol
Abstract: Techniques are disclosed relating to providing audio prompts. In one embodiment, a computing device includes a display, an audio circuit coupled to a speaker, first and second processors, and memory. The memory has first program instructions executable by the first processor to provide, via a first operating system of the computing device, a visual prompt to the display to cause the display to present the visual prompt to a user and send, to the second processor, a request to provide an audio prompt corresponding to the visual prompt via the speaker to the user. The computing device also includes memory having second program instructions executable by the second processor to, in response to the request, provide, via a second operating system, an instruction to the audio circuit to play the audio prompt via the speaker.
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