公开(公告)号：US20240143530A1

公开(公告)日：2024-05-02

申请号：US18404449

申请日：2024-01-04

Applicant: Apple Inc.

Inventor： Brett D. George ,  Rohit K. Gupta ,  Do Kyung Kim ,  Paul W. Glendenning

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F2213/28

Abstract: Techniques for improving the handling of peripherals in a computer system, including through the use of a DMA control circuit that helps manage the flow of data between memory and the peripherals via an intermediate storage buffer. The DMA control circuit is configured to control timing of DMA transfers between sample buffers in the memory and the intermediate storage buffer. The DMA control circuit may output a priority value of the DMA control circuit for accesses to memory, where the priority value based on stored quality of service (QoS) information and current channel data buffer levels for different DMA channels. The DMA control circuit may separately arbitrate between multiple active transmit and receive channels. Still further, the DMA control circuit may store, for a given data transfer over a particular DMA channel, timestamp information indicative of completion of the DMA and peripheral-side operations.

公开(公告)号：US11886365B2

公开(公告)日：2024-01-30

申请号：US17475074

申请日：2021-09-14

Applicant: Apple Inc.

Inventor： Brett D. George ,  Rohit K. Gupta ,  Do Kyung Kim ,  Paul W. Glendenning

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F2213/28

Abstract: Techniques for improving the handling of peripherals in a computer system, including through the use of a DMA control circuit that helps manage the flow of data between memory and the peripherals via an intermediate storage buffer. The DMA control circuit is configured to control timing of DMA transfers between sample buffers in the memory and the intermediate storage buffer. The DMA control circuit may output a priority value of the DMA control circuit for accesses to memory, where the priority value based on stored quality of service (QoS) information and current channel data buffer levels for different DMA channels. The DMA control circuit may separately arbitrate between multiple active transmit and receive channels. Still further, the DMA control circuit may store, for a given data transfer over a particular DMA channel, timestamp information indicative of completion of the DMA and peripheral-side operations.

公开(公告)号：US20220083486A1

公开(公告)日：2022-03-17

申请号：US17475074

申请日：2021-09-14

Applicant: Apple Inc.

Inventor： Brett D. George ,  Rohit K. Gupta ,  Do Kyung Kim ,  Paul W. Glendenning

IPC: G06F13/28

Abstract: Techniques for improving the handling of peripherals in a computer system, including through the use of a DMA control circuit that helps manage the flow of data between memory and the peripherals via an intermediate storage buffer. The DMA control circuit is configured to control timing of DMA transfers between sample buffers in the memory and the intermediate storage buffer. The DMA control circuit may output a priority value of the DMA control circuit for accesses to memory, where the priority value based on stored quality of service (QoS) information and current channel data buffer levels for different DMA channels. The DMA control circuit may separately arbitrate between multiple active transmit and receive channels. Still further, the DMA control circuit may store, for a given data transfer over a particular DMA channel, timestamp information indicative of completion of the DMA and peripheral-side operations.