公开(公告)号：US20240061466A1

公开(公告)日：2024-02-22

申请号：US18500716

申请日：2023-11-02

Applicant: Apple Inc.

Inventor： Harry K. Ng ,  Alvin K. Ng ,  Katherine E. Tong ,  Tyler S. Bushnell ,  Amin M. Younes ,  Benjamin S. Bustle ,  Christopher D. Jones ,  James R. Wilson

IPC: G06F1/16 ,  G09G3/3208 ,  G06F3/044

CPC classification number: G06F1/1626 ,  G09G3/3208 ,  G06F3/044 ,  G09G2300/046

Abstract: An electronic device display may have an inner layer with a pixel array for displaying images and an outer layer with an array of light modulator cells operable in transparent and light-blocking modes. Force sensor and touch sensor circuitry may be used to gather user input such as information on finger pressure or stylus input applied to a location on the display. A block of the cells may be placed into a transparent mode to form a transparent window based on information from the sensor circuitry. Images on the pixel array may be viewed through the window. In another mode of operation, images can be displayed by adjusting the cells of the light modulator layer and backlight illumination may be provided by the pixel array. A camera and a flash or other optical components may be overlapped by an adjustable shutter.

公开(公告)号：US11808820B1

公开(公告)日：2023-11-07

申请号：US17878952

申请日：2022-08-02

Applicant: APPLE INC.

Inventor： Stephen C. Sherbrook ,  Alvin K. Ng ,  Anthony Da Costa

IPC: G01R31/40 ,  G01R19/00

CPC classification number: G01R31/40 ,  G01R19/0092

Abstract: A system includes a first connection configured to allow current flow between a first node and a second node through a first transistor when it is enabled, and a first diode configured to allow current flow between the first node and the second node when the first transistor is disabled. A second connection is configured to allow current flow between the first node and the second node through a second transistor when it is enabled, and a second diode configured to allow current flow between the first node and the second node when the second transistor is disabled. A fault detection circuit is configured to test the first connection by detection of current flow on the second connection with the second transistor disabled, and is configured to test the second connection by detection of current flow on the first connection with the first transistor disabled.