公开(公告)号：US20240322556A1

公开(公告)日：2024-09-26

申请号：US18219310

申请日：2023-07-07

Applicant: Apple Inc.

Inventor： Anthony Da Costa ,  Stephen C Sherbrook ,  Kevin J White

IPC: H02H7/22 ,  H02H1/00

CPC classification number: H02H7/22 ,  H02H1/0015

Abstract: DC power systems operating at 48 V and higher may increase risk for sustained electrical arcs. In particular, a series arc may be formed and sustained when a connection fails open between a power source and an electrical load that continues to operate while the arc is present. In some applications, many or all modules may already be interconnected via network links, such as a Controller Area Network (CAN) bus, a Local Interconnect Network (LIN) bus, Ethernet, and so on. An arc detection and mitigation system may leverage an existing communication network to enable arc detection and mitigation while avoiding excessive additive costs.

公开(公告)号：US11808820B1

公开(公告)日：2023-11-07

申请号：US17878952

申请日：2022-08-02

Applicant: APPLE INC.

Inventor： Stephen C. Sherbrook ,  Alvin K. Ng ,  Anthony Da Costa

IPC: G01R31/40 ,  G01R19/00

CPC classification number: G01R31/40 ,  G01R19/0092

Abstract: A system includes a first connection configured to allow current flow between a first node and a second node through a first transistor when it is enabled, and a first diode configured to allow current flow between the first node and the second node when the first transistor is disabled. A second connection is configured to allow current flow between the first node and the second node through a second transistor when it is enabled, and a second diode configured to allow current flow between the first node and the second node when the second transistor is disabled. A fault detection circuit is configured to test the first connection by detection of current flow on the second connection with the second transistor disabled, and is configured to test the second connection by detection of current flow on the first connection with the first transistor disabled.