公开(公告)号：US20140372734A1

公开(公告)日：2014-12-18

申请号：US13916417

申请日：2013-06-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Joseph Lee Greathouse ,  Anton Chernoff

IPC: G06F9/38

CPC classification number: G06F11/30 ,  G06F9/3005 ,  G06F11/3003 ,  G06F11/3471 ,  G06F11/3476 ,  G06F11/3648 ,  G06F2201/865

Abstract: A processor, a method and a computer-readable medium for recording branch addresses are provided. The processor comprises hardware registers and first and second circuitry. The first circuitry is configured to store a first address associated with a branch instruction in the hardware registers. The first circuitry is further configured to store a second address that indicates where the processor execution is redirected to as a result of the branch instruction in the hardware registers. The second circuitry is configured to, in response to a second instruction, retrieve a value of at least one of the registers. The second instruction can be a user-level instruction.

Abstract translation: 提供了用于记录分支地址的处理器，方法和计算机可读介质。 处理器包括硬件寄存器和第一和第二电路。 第一电路被配置为在硬件寄存器中存储与分支指令相关联的第一地址。 第一电路还被配置为作为硬件寄存器中的分支指令的结果存储指示处理器执行被重定向到哪里的第二地址。 第二电路被配置为响应于第二指令检索至少一个寄存器的值。 第二条指令可以是用户级指令。

公开(公告)号：US09372773B2

公开(公告)日：2016-06-21

申请号：US13916417

申请日：2013-06-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Joseph Lee Greathouse ,  Anton Chernoff

IPC: G06F9/44 ,  G06F11/30 ,  G06F9/30

CPC classification number: G06F11/30 ,  G06F9/3005 ,  G06F11/3003 ,  G06F11/3471 ,  G06F11/3476 ,  G06F11/3648 ,  G06F2201/865

Abstract: A processor, a method and a computer-readable medium for recording branch addresses are provided. The processor comprises hardware registers and first and second circuitry. The first circuitry is configured to store a first address associated with a branch instruction in the hardware registers. The first circuitry is further configured to store a second address that indicates where the processor execution is redirected to as a result of the branch instruction in the hardware registers. The second circuitry is configured to, in response to a second instruction, retrieve a value of at least one of the registers. The second instruction can be a user-level instruction.

Abstract translation: 提供了用于记录分支地址的处理器，方法和计算机可读介质。 处理器包括硬件寄存器和第一和第二电路。 第一电路被配置为在硬件寄存器中存储与分支指令相关联的第一地址。 第一电路还被配置为作为硬件寄存器中的分支指令的结果存储指示处理器执行被重定向到哪里的第二地址。 第二电路被配置为响应于第二指令检索至少一个寄存器的值。 第二条指令可以是用户级指令。

公开(公告)号：US20140258688A1

公开(公告)日：2014-09-11

申请号：US13789233

申请日：2013-03-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mauricio Breternitz ,  Anton Chernoff ,  Keith A. Lowery

IPC: G06F9/30

CPC classification number: G06F11/3428 ,  G06F11/3466 ,  G06F11/348

Abstract: Methods and systems are provided for generating a benchmark representative of a reference process. One method involves obtaining execution information for a subset of the plurality of instructions of the reference process from a pipeline of a processing module during execution of those instructions by the processing module, determining performance characteristics quantifying the execution behavior of the reference process based on the execution information, and generating the benchmark process that mimics the quantified execution behavior of the reference process based on the performance characteristics.

Abstract translation: 提供了用于生成参考过程的基准代表的方法和系统。 一种方法包括在处理模块执行这些指令期间从处理模块的流水线获取参考过程的多个指令的子集的执行信息，基于执行来确定量化参考进程的执行行为的性能特征 信息，以及基于性能特征生成模拟参考过程的量化执行行为的基准过程。

公开(公告)号：US20150106574A1

公开(公告)日：2015-04-16

申请号：US14053957

申请日：2013-10-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Anton Chernoff

IPC: G06F3/06

CPC classification number: G06F15/7821 ,  G06F9/3881 ,  G06F2003/0697 ,  Y02D10/12 ,  Y02D10/13

Abstract: The described embodiments include a computing device that comprises at least one memory die having memory circuits and memory die processing circuits, and a logic die coupled to the at least one memory die, the logic die having logic die processing circuits. In the described embodiments, the memory die processing circuits are configured to perform memory die processing operations on data retrieved from or destined for the memory circuits and the logic die processing circuits are configured to perform logic die processing operations on data retrieved from or destined for the memory circuits.

Abstract translation: 所描述的实施例包括计算设备，其包括具有存储器电路和存储器管芯处理电路的至少一个存储器管芯，以及耦合到至少一个存储器管芯的逻辑管芯，所述逻辑管芯具有逻辑管芯处理电路。 在所描述的实施例中，存储器管芯处理电路被配置为对从存储器电路检索或去往存储器电路的数据执行存储器管芯处理操作，并且逻辑管芯处理电路被配置为对从或从 存储电路。