Semiconductor device having multi access level and access control method thereof
    1.
    发明授权
    Semiconductor device having multi access level and access control method thereof 有权
    具有多路访问级别及其访问控制方法的半导体器件

    公开(公告)号:US08347116B2

    公开(公告)日:2013-01-01

    申请号:US12796110

    申请日:2010-06-08

    IPC分类号: G06F12/14 G06F12/00

    CPC分类号: G06F21/74 G06F12/1491

    摘要: An access control method of a semiconductor device includes providing an inputted password as an input of a hash operator; performing a hash operation in the hash operator and outputting a first hash value; controlling the hash operator so that the hash operation is repeatedly performed in the hash operator by providing the first hash value as an input of the hash operator when the first hash value and a second hash value stored in a nonvolatile memory do not coincide; and setting an access level with respect to the inner circuit according to the repetition number of times of the hash operation of the hash operator when the first and second hash values coincide.

    摘要翻译: 一种半导体器件的访问控制方法,包括提供输入的密码作为散列算子的输入; 在所述散列算子中执行哈希操作并输出第一散列值; 控制所述散列算子,使得当所述第一散列值和存储在非易失性存储器中的第二散列值不一致时,通过提供所述第一散列值作为所述散列算子的输入,在所述散列算子中重复执行所述散列操作; 以及当所述第一和第二散列值一致时,根据所述散列算子的散列操作的重复次数,设置相对于所述内部电路的访问级别。

    Apparatus and method of authenticating Joint Test Action Group (JTAG)
    2.
    发明申请
    Apparatus and method of authenticating Joint Test Action Group (JTAG) 有权
    联合测试行动小组(JTAG)认证的设备和方法

    公开(公告)号:US20100153797A1

    公开(公告)日:2010-06-17

    申请号:US12653082

    申请日:2009-12-08

    IPC分类号: G01R31/3177 G06F11/25

    摘要: In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed.

    摘要翻译: 在包括联合测试动作组(JTAG)认证装置的装置和使用该装置的JTAG认证方法中,该装置包括联合测试动作组(JTAG)认证装置,该装置包括确定是否存取的JTAG接入电路 根据预定协议的JTAG兼容设备,其管理所述JTAG兼容设备和所述设备,其中所述JTAG接入电路至少一个使内部总线和内部单元中的至少一个失效,并激活所述内部 总线线路和内部单元,根据是否访问JTAG兼容设备。

    APPARATUS AND METHOD OF AUTHENTICATING JOINT TEST ACTION GROUP (JTAG)
    3.
    发明申请
    APPARATUS AND METHOD OF AUTHENTICATING JOINT TEST ACTION GROUP (JTAG) 审中-公开
    联合测试行动小组(JTAG)的设备及方法

    公开(公告)号:US20120060067A1

    公开(公告)日:2012-03-08

    申请号:US13291324

    申请日:2011-11-08

    IPC分类号: G01R31/3177 G06F11/25

    摘要: In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed.

    摘要翻译: 在包括联合测试动作组(JTAG)认证装置的装置和使用该装置的JTAG认证方法中,该装置包括联合测试动作组(JTAG)认证装置,该装置包括确定是否存取的JTAG接入电路 根据预定协议的JTAG兼容设备,其管理所述JTAG兼容设备和所述设备,其中所述JTAG接入电路至少一个使内部总线和内部单元中的至少一个失效,并激活所述内部 总线线路和内部单元,根据是否访问JTAG兼容设备。

    SEMICONDUCTOR DEVICE HAVING MULTI ACCESS LEVEL AND ACCESS CONTROL METHOD THEREOF
    4.
    发明申请
    SEMICONDUCTOR DEVICE HAVING MULTI ACCESS LEVEL AND ACCESS CONTROL METHOD THEREOF 有权
    具有多个访问级别的半导体器件及其访问控制方法

    公开(公告)号:US20100332783A1

    公开(公告)日:2010-12-30

    申请号:US12796110

    申请日:2010-06-08

    IPC分类号: G06F12/14 G06F12/00

    CPC分类号: G06F21/74 G06F12/1491

    摘要: An access control method of a semiconductor device includes providing an inputted password as an input of a hash operator; performing a hash operation in the hash operator and outputting a first hash value; controlling the hash operator so that the hash operation is repeatedly performed in the hash operator by providing the first hash value as an input of the hash operator when the first hash value and a second hash value stored in a nonvolatile memory do not coincide; and setting an access level with respect to the inner circuit according to the repetition number of times of the hash operation of the hash operator when the first and second hash values coincide.

    摘要翻译: 一种半导体器件的访问控制方法,包括提供输入的密码作为散列算子的输入; 在所述散列算子中执行哈希操作并输出第一散列值; 控制所述散列算子,使得当所述第一散列值和存储在非易失性存储器中的第二散列值不一致时,通过提供所述第一散列值作为所述散列算子的输入,在所述散列算子中重复执行所述散列操作; 以及当所述第一和第二散列值一致时,根据所述散列算子的散列操作的重复次数,设置相对于所述内部电路的访问级别。

    ELECTRONIC SYSTEM HAVING INTEGRITY VERIFICATION DEVICE
    5.
    发明申请
    ELECTRONIC SYSTEM HAVING INTEGRITY VERIFICATION DEVICE 有权
    具有完整性验证装置的电子系统

    公开(公告)号:US20150254458A1

    公开(公告)日:2015-09-10

    申请号:US14638862

    申请日:2015-03-04

    IPC分类号: G06F21/57

    摘要: Provided are an electronic system, an integrity verification device, and a method of performing an integrity verification operation. The electronic system includes: a memory device; a processor configured to provide a plurality of configuration records corresponding to a plurality of verification data stored in the memory device, each of the configuration records including a start address, a data length, and a reference hash value for a corresponding verification data; and an integrity verification device configured to: store the configuration records, select a configuration record, directly access the memory device to read verification data, corresponding to the selected configuration record, based on the start address and the data length included in the selected configuration record, perform a hash operation on the verification data to obtain a verification hash value, and output an interrupt signal based on the verification hash value and the reference hash value comprised in the selected configuration record.

    摘要翻译: 提供电子系统,完整性验证装置和执行完整性验证操作的方法。 电子系统包括:存储装置; 处理器,其被配置为提供与存储在所述存储器件中的多个验证数据相对应的多个配置记录,所述配置记录包括相应验证数据的起始地址,数据长度和参考散列值; 以及完整性验证装置,被配置为:基于包括在所选配置记录中的开始地址和数据长度,存储配置记录,选择配置记录,直接访问存储设备以读取与所选配置记录相对应的验证数据 对验证数据执行哈希操作以获得验证散列值,并且基于所选配置记录中包含的验证散列值和参考散列值输出中断信号。

    ELECTRONIC DEVICE BOOTED UP WITH SECURITY, A HASH COMPUTING METHOD, AND A BOOT-UP METHOD THEREOF
    6.
    发明申请
    ELECTRONIC DEVICE BOOTED UP WITH SECURITY, A HASH COMPUTING METHOD, AND A BOOT-UP METHOD THEREOF 审中-公开
    具有安全性的电子设备,散列计算方法及其启动方法

    公开(公告)号:US20090144559A1

    公开(公告)日:2009-06-04

    申请号:US12249295

    申请日:2008-10-10

    IPC分类号: G06F21/00

    CPC分类号: G06F21/575

    摘要: A method for authenticating a public key to execute a process with security, including: invoking a process; reading a public key from a first source; calculating a hash value of the public key with a block encryption algorithm, wherein part of the public key is an initial input value of the block encryption algorithm; reading a hash value from a second source; comparing the calculated hash value to the read hash value to determine if the public key is authentic; and executing the process if the public key is authentic.

    摘要翻译: 一种用于认证公钥以执行具有安全性的过程的方法,包括:调用进程; 从第一个来源读取公钥; 使用块加密算法计算公钥的哈希值,其中公钥的一部分是块加密算法的初始输入值; 从第二个源读取哈希值; 将所计算的散列值与读取的散列值进行比较,以确定公钥是否是真实的; 并且如果公钥是真实的,则执行该过程。

    Apparatus and method of authenticating joint test action group (JTAG)
    7.
    发明授权
    Apparatus and method of authenticating joint test action group (JTAG) 有权
    认证联合测试动作组(JTAG)的设备和方法

    公开(公告)号:US08056142B2

    公开(公告)日:2011-11-08

    申请号:US12653082

    申请日:2009-12-08

    IPC分类号: G06F7/04 G06F17/30 H04N7/16

    摘要: In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed.

    摘要翻译: 在包括联合测试动作组(JTAG)认证装置的装置和使用该装置的JTAG认证方法中,该装置包括联合测试动作组(JTAG)认证装置,该装置包括确定是否存取的JTAG接入电路 根据预定协议的JTAG兼容设备,其管理所述JTAG兼容设备和所述设备,其中所述JTAG接入电路至少一个使内部总线和内部单元中的至少一个失效,并激活所述内部 总线线路和内部单元,根据是否访问JTAG兼容设备。