知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

10 条记录 (耗时 0.011 秒)

    Sigma-delta analog-to-digital converter and solid-state image pickup device
    1.
    发明授权
    Sigma-delta analog-to-digital converter and solid-state image pickup device 有权
    Sigma-delta模数转换器和固态图像拾取器件

    公开(公告)号：US07773018B2

    公开(公告)日：2010-08-10

    申请号：US12453845

    申请日：2009-05-26

    申请人： Youngcheol Chae ,  In Hee Lee ,  Gunhee Han ,  Seog Heon Ham

    发明人： Youngcheol Chae ,  In Hee Lee ,  Gunhee Han ,  Seog Heon Ham

    IPC分类号： H03M3/00

    CPC分类号： H03M3/384 ,  H03M3/424

    摘要： A sigma-delta analog-to-digital converter may include a sigma-delta modulator and a decimation filter. The sigma-delta modulator may convert a first analog input signal into a first bit stream having a first pattern using sigma-delta modulation and convert a second analog input signal into a second bit stream having a second pattern using the sigma-delta modulation. The decimation filter may integrate the number of bits having a particular value in the first bit stream, output a first digital value, calculate a bitwise complement value of the first digital value, integrate the number of bits having the particular value in the second bit stream with the bitwise complement value of the first digital value as an initial value of a second digital value, and output the second digital value.

    摘要翻译： Σ-Δ模数转换器可以包括Σ-Δ调制器和抽取滤波器。 Σ-Δ调制器可以使用Σ-Δ调制将第一模拟输入信号转换成具有第一模式的第一比特流，并且使用Σ-Δ调制将第二模拟输入信号转换成具有第二模式的第二比特流。 抽取滤波器可以将具有特定值的比特数量集成在第一比特流中，输出第一数字值，计算第一数字值的按位补码，将具有特定值的比特数集成在第二比特流中 以第一数字值的按位补码作为第二数字值的初始值，并输出第二数字值。

    APPARATUS AND METHOD FOR SIGMA-DELTA ANALOG TO DIGITAL CONVERSION
    2.
    发明申请
    APPARATUS AND METHOD FOR SIGMA-DELTA ANALOG TO DIGITAL CONVERSION 有权
    SIGMA-DELTA模拟数字转换的装置和方法

    公开(公告)号：US20090261998A1

    公开(公告)日：2009-10-22

    申请号：US12427303

    申请日：2009-04-21

    申请人： Youngcheol Chae ,  In Hee Lee ,  Jimin Cheon ,  Gunhee Han ,  Seog Heon Ham

    发明人： Youngcheol Chae ,  In Hee Lee ,  Jimin Cheon ,  Gunhee Han ,  Seog Heon Ham

    IPC分类号： H03M1/12 ,  H03M1/34 ,  H03M3/00 ,  H03M1/06

    CPC分类号： H03M3/46 ,  H03M1/56 ,  H03M3/43 ,  H03M3/456

    摘要： A method and apparatus are provided for sigma-delta (ΣΔ) analog to digital conversion, the method including receiving an analog signal, sampling the received signal, comparing the sampled signal with a constant reference voltage, providing at least one high-order bit responsive to the constant reference comparison, comparing the sampled signal with a variable reference voltage, providing at least one low-order bit responsive to the variable reference comparison, and combining the at least one high-order bit with the at least one low-order bit; and the apparatus including a comparator, a first ADC portion supplying the comparator with a constant reference voltage for providing at least one high-order bit, and a second ADC portion supplying the comparator with a variable reference voltage for providing at least One low-order bit.

    摘要翻译： 提供了一种用于Σ-Δ（SigmaDelta）模数转换的方法和装置，该方法包括接收模拟信号，对接收信号进行采样，将采样信号与恒定参考电压进行比较，提供至少一个高阶位响应 对所述恒定参考比较进行比较，将所述采样信号与可变参考电压进行比较，提供响应于所述可变参考比较的至少一个低阶位，以及将所述至少一个高位位与所述至少一个低位位 ; 并且所述装置包括比较器，向所述比较器提供用于提供至少一个高位的恒定参考电压的第一ADC部分和向比较器提供可变参考电压的第二ADC部分，用于提供至少一个低阶 位。

    Switched capacitor circuit with inverting amplifier and offset unit
    3.
    发明申请
    Switched capacitor circuit with inverting amplifier and offset unit 有权
    具有反相放大器和偏移单元的开关电容器电路

    公开(公告)号：US20080116966A1

    公开(公告)日：2008-05-22

    申请号：US11986345

    申请日：2007-11-21

    申请人： Youngcheol Chae ,  Gunhee Han ,  Seog-Heon Ham

    发明人： Youngcheol Chae ,  Gunhee Han ,  Seog-Heon Ham

    IPC分类号： H03K5/00

    CPC分类号： H03H19/004 ,  H03M3/356 ,  H03M3/43 ,  H03M3/456

    摘要： A switched capacitor circuit includes an amplifier, a charging unit, an offset unit, and an integrating unit. The charging unit is coupled between an input node and a first node, and is for accumulating charge corresponding to an input signal during a sampling mode. The offset unit is coupled between the first node and an input of the amplifier, and is for maintaining the first node to be a virtual ground during an integrating mode. The integrating unit is coupled between the first node and an output of the amplifier, and is for receiving charge from the charging unit during the integrating mode.

    摘要翻译： 开关电容电路包括放大器，充电单元，偏移单元和积分单元。 充电单元耦合在输入节点和第一节点之间，并且用于在采样模式期间累加对应于输入信号的电荷。 偏移单元耦合在第一节点和放大器的输入之间，并且用于在积分模式期间将第一节点维持为虚拟地面。 积分单元耦合在第一节点和放大器的输出端之间，用于在积分模式期间从充电单元接收电荷。

    Decimation filters, analog-to-digital converters including the same, and image sensors including the converters
    5.
    发明授权
    Decimation filters, analog-to-digital converters including the same, and image sensors including the converters 有权
    抽取滤波器，包括相同的模数转换器和包括转换器的图像传感器

    公开(公告)号：US08233068B2

    公开(公告)日：2012-07-31

    申请号：US12453593

    申请日：2009-05-15

    申请人： Youngcheol Chae ,  In Hee Lee ,  Jimin Cheon ,  Gunhee Han ,  Seog Heon Ham

    发明人： Youngcheol Chae ,  In Hee Lee ,  Jimin Cheon ,  Gunhee Han ,  Seog Heon Ham

    IPC分类号： H04N5/335

    CPC分类号： H04N5/37455 ,  H03H17/0664 ,  H03M3/424 ,  H03M3/462

    摘要： An image sensor includes an analog-to-digital converter (ADC) and a decimation filter. The decimation filter includes a first digital data generator and a second digital data generator. The first digital data generator is configured to integrate sigma-delta modulated M-bit pixel data and output N-bit pixel data based on an integration result. The second digital data generator is configured to integrate the N-bit pixel data, generate P-bit pixel data based on an integration result, and output the P-bit pixel data as decimated data.

    摘要翻译： 图像传感器包括模数转换器（ADC）和抽取滤波器。 抽取滤波器包括第一数字数据发生器和第二数字数据发生器。 第一数字数据发生器被配置为基于积分结果来集成Σ-Δ调制的M位像素数据和输出N位像素数据。 第二数字数据发生器被配置为集成N位像素数据，基于积分结果产生P位像素数据，并将P位像素数据输出为抽取数据。

    Sigma-delta analog-to-digital converter and solid-state image pickup device
    6.
    发明申请
    Sigma-delta analog-to-digital converter and solid-state image pickup device 有权
    Sigma-delta模数转换器和固态图像拾取器件

    公开(公告)号：US20090289823A1

    公开(公告)日：2009-11-26

    申请号：US12453845

    申请日：2009-05-26

    申请人： Youngcheol Chae ,  In Hee Lee ,  Gunhee Han ,  Seog Heon Ham

    发明人： Youngcheol Chae ,  In Hee Lee ,  Gunhee Han ,  Seog Heon Ham

    IPC分类号： H03M3/00

    CPC分类号： H03M3/384 ,  H03M3/424

    摘要： A sigma-delta analog-to-digital converter may include a sigma-delta modulator and a decimation filter. The sigma-delta modulator may convert a first analog input signal into a first bit stream having a first pattern using sigma-delta modulation and convert a second analog input signal into a second bit stream having a second pattern using the sigma-delta modulation. The decimation filter may integrate the number of bits having a particular value in the first bit stream, output a first digital value, calculate a bitwise complement value of the first digital value, integrate the number of bits having the particular value in the second bit stream with the bitwise complement value of the first digital value as an initial value of a second digital value, and output the second digital value.

    摘要翻译： Σ-Δ模数转换器可以包括Σ-Δ调制器和抽取滤波器。 Σ-Δ调制器可以使用Σ-Δ调制将第一模拟输入信号转换成具有第一模式的第一比特流，并且使用Σ-Δ调制将第二模拟输入信号转换成具有第二模式的第二比特流。 抽取滤波器可以将具有特定值的比特数量集成在第一比特流中，输出第一数字值，计算第一数字值的按位补码，将具有特定值的比特数集成在第二比特流中 以第一数字值的按位补码作为第二数字值的初始值，并输出第二数字值。

    Apparatus and method for sigma-delta analog to digital conversion
    8.
    发明授权
    Apparatus and method for sigma-delta analog to digital conversion 有权
    用于Σ-Δ模数转换的装置和方法

    公开(公告)号：US07916061B2

    公开(公告)日：2011-03-29

    申请号：US12427303

    申请日：2009-04-21

    申请人： Youngcheol Chae ,  In Hee Lee ,  Jimin Cheon ,  Gunhee Han ,  Seog Heon Ham

    发明人： Youngcheol Chae ,  In Hee Lee ,  Jimin Cheon ,  Gunhee Han ,  Seog Heon Ham

    IPC分类号： H03M1/12

    CPC分类号： H03M3/46 ,  H03M1/56 ,  H03M3/43 ,  H03M3/456

    摘要： A method and apparatus are provided for sigma-delta (ΣΔ) analog to digital conversion, the method including receiving an analog signal, sampling the received signal, comparing the sampled signal with a constant reference voltage, providing at least one high-order bit responsive to the constant reference comparison, comparing the sampled signal with a variable reference voltage, providing at least one low-order bit responsive to the variable reference comparison, and combining the at least one high-order bit with the at least one low-order bit; and the apparatus including a comparator, a first ADC portion supplying the comparator with a constant reference voltage for providing at least one high-order bit, and a second ADC portion supplying the comparator with a variable reference voltage for providing at least one low-order bit.

    摘要翻译： 提供了一种用于Σ-Δ（＆Sgr＆amp; Dgr）模数转换的方法和装置，该方法包括接收模拟信号，对接收信号进行采样，将采样信号与恒定参考电压进行比较， 响应于常数参考比较，将采样信号与可变参考电压进行比较，提供响应于可变参考比较的至少一个低阶位，以及将至少一个高位位与至少一个低位比较 顺序位 并且所述装置包括比较器，为比较器提供用于提供至少一个高位的恒定参考电压的第一ADC部分和向比较器提供可变参考电压的第二ADC部分，用于提供至少一个低阶 位。

    Switched capacitor circuit with inverting amplifier and offset unit
    9.
    发明授权
    Switched capacitor circuit with inverting amplifier and offset unit 有权
    具有反相放大器和偏移单元的开关电容器电路

    公开(公告)号：US07800427B2

    公开(公告)日：2010-09-21

    申请号：US11986345

    申请日：2007-11-21

    申请人： Youngcheol Chae ,  Gunhee Han ,  Seog-Heon Ham

    发明人： Youngcheol Chae ,  Gunhee Han ,  Seog-Heon Ham

    IPC分类号： G06G7/184 ,  H03M3/02

    CPC分类号： H03H19/004 ,  H03M3/356 ,  H03M3/43 ,  H03M3/456

    摘要： A switched capacitor circuit includes an amplifier, a charging unit, an offset unit, and an integrating unit. The charging unit is coupled between an input node and a first node, and is for accumulating charge corresponding to an input signal during a sampling mode. The offset unit is coupled between the first node and an input of the amplifier, and is for maintaining the first node to be a virtual ground during an integrating mode. The integrating unit is coupled between the first node and an output of the amplifier, and is for receiving charge from the charging unit during the integrating mode.

    摘要翻译： 开关电容电路包括放大器，充电单元，偏移单元和积分单元。 充电单元耦合在输入节点和第一节点之间，并且用于在采样模式期间累加对应于输入信号的电荷。 偏移单元耦合在第一节点和放大器的输入之间，并且用于在积分模式期间将第一节点维持为虚拟地面。 积分单元耦合在第一节点和放大器的输出端之间，用于在积分模式期间从充电单元接收电荷。

    Decimation filters, analog-to-digital converters including the same, and image sensors including the converters
    10.
    发明申请
    Decimation filters, analog-to-digital converters including the same, and image sensors including the converters 有权
    抽取滤波器，包括相同的模数转换器和包括转换器的图像传感器

    公开(公告)号：US20090295956A1

    公开(公告)日：2009-12-03

    申请号：US12453593

    申请日：2009-05-15

    申请人： Youngcheol Chae ,  In Hee Lee ,  Jimin Cheon ,  Gunhee Han ,  Seog Heon Ham

    发明人： Youngcheol Chae ,  In Hee Lee ,  Jimin Cheon ,  Gunhee Han ,  Seog Heon Ham

    IPC分类号： H04N3/14 ,  G06F17/17 ,  H03M1/12

    CPC分类号： H04N5/37455 ,  H03H17/0664 ,  H03M3/424 ,  H03M3/462

    摘要： An image sensor includes an analog-to-digital converter (ADC) and a decimation filter. The decimation filter includes a first digital data generator and a second digital data generator. The first digital data generator is configured to integrate sigma-delta modulated M-bit pixel data and output N-bit pixel data based on an integration result. The second digital data generator is configured to integrate the N-bit pixel data, generate P-bit pixel data based on an integration result, and output the P-bit pixel data as decimated data.

    摘要翻译： 图像传感器包括模数转换器（ADC）和抽取滤波器。 抽取滤波器包括第一数字数据发生器和第二数字数据发生器。 第一数字数据发生器被配置为基于积分结果来集成Σ-Δ调制的M位像素数据和输出N位像素数据。 第二数字数据发生器被配置为集成N位像素数据，基于积分结果产生P位像素数据，并将P位像素数据输出为抽取数据。