公开(公告)号：US06960500B2

公开(公告)日：2005-11-01

申请号：US10777233

申请日：2004-02-11

申请人： You-Cheol Shin ,  Kyu-Charn Park ,  Won-Hong Lee ,  Jung-Dal Choi

发明人： You-Cheol Shin ,  Kyu-Charn Park ,  Won-Hong Lee ,  Jung-Dal Choi

IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/82 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/04 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.

摘要翻译： 一种半导体器件包括多个栅极线，其由在多个晶体管中用作栅电极的线形构成，并且通过栅极绝缘层与基板分离，各自具有上金属硅化物层; 以及仅通过进行杂质注入工艺而在所述栅极线之间的衬底上形成的多个源极/漏极区域。

公开(公告)号：US06784481B2

公开(公告)日：2004-08-31

申请号：US10098875

申请日：2002-03-15

申请人： You-Cheol Shin ,  Jong-Woo Park ,  Jung-Dal Choi

发明人： You-Cheol Shin ,  Jong-Woo Park ,  Jung-Dal Choi

IPC分类号： H01L2976

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792

摘要： A flash memory having a charge-storage dielectric layer. According to one embodiment, charge-storage dielectric layers are formed over the first and second active regions. The charge-storage layer over the first active region is not connected to the charge-storage layer over the second active region. A gate line overlies the charge-storage layer and extends across the first and second active regions and the isolation region. The charge-storage layer can be formed only where a gate line intersects an active region of a semiconductor substrate, not on an isolation region. Thus, undesirable influence or disturbance from adjacent memory cells can be avoided.

摘要翻译： 具有电荷存储介电层的闪速存储器。 根据一个实施例，电荷存储电介质层形成在第一和第二有源区上。 第一有源区上的电荷存储层在第二有源区上并未连接到电荷存储层。 栅极线覆盖电荷存储层并且延伸穿过第一和第二有源区域和隔离区域。 电荷存储层只能在栅极线与半导体衬底的有源区相交而不在隔离区上形成。 因此，可以避免来自相邻存储单元的不期望​​的影响或干扰。

公开(公告)号：US06720579B2

公开(公告)日：2004-04-13

申请号：US10041732

申请日：2002-01-07

申请人： You-Cheol Shin ,  Kyu-Charn Park ,  Won-Hong Lee ,  Jung-Dal Choi

发明人： You-Cheol Shin ,  Kyu-Charn Park ,  Won-Hong Lee ,  Jung-Dal Choi

IPC分类号： H01L27108

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.

摘要翻译： 一种半导体器件包括多个栅极线，其由在多个晶体管中用作栅电极的线形构成，并且通过栅极绝缘层与基板分离，各自具有上金属硅化物层; 以及仅通过进行杂质注入工艺而在所述栅极线之间的衬底上形成的多个源极/漏极区域。

公开(公告)号：US07144790B2

公开(公告)日：2006-12-05

申请号：US10407115

申请日：2003-04-04

申请人： You-Cheol Shin

发明人： You-Cheol Shin

IPC分类号： H01L21/762

CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/76232

摘要： A shallow trench isolation type semiconductor device is described, which includes a trench having a flexure in a bottom thereof. The flexure has a step difference of about 100 Å or more, and is preferably made at a middle area. Conventionally, a gate insulating layer includes a thin area of about 100 Å or less and a thick area of about 200 Å or more. On the basis of a bottom of a trench peripheral region, a middle part of the flexure may be concave or convex. Particularly, the foregoing device can effectively be applied to a self-aligned flash memory in which a width of a trench between one active region and another is about 3 micrometers or less.

公开(公告)号：US06784055B2

公开(公告)日：2004-08-31

申请号：US10418701

申请日：2003-04-18

申请人： You-Cheol Shin ,  Jong-Woo Park ,  Jung-Dal Choi

发明人： You-Cheol Shin ,  Jong-Woo Park ,  Jung-Dal Choi

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792

摘要： A flash memory having a charge-storage dielectric layer and a method for forming the same are provided. According to one embodiment, charge-storage dielectric layers are formed over the first and second active regions. The charge-storage layer over the first active region is not connected to the charge-storage layer over the second active region. A gate line overlies the charge-storage layer and extends across the first and second active regions and the isolation region. The charge-storage layer can be formed only where a gate line intersects an active region of a semiconductor substrate, not on an isolation region. Thus, undesirable influence or disturbance from adjacent memory cells can be avoided.

摘要翻译： 提供具有电荷存储介质层的闪速存储器及其形成方法。 根据一个实施例，电荷存储电介质层形成在第一和第二有源区上。 第一有源区上的电荷存储层在第二有源区上并未连接到电荷存储层。 栅极线覆盖电荷存储层并且延伸穿过第一和第二有源区域和隔离区域。 电荷存储层只能在栅极线与半导体衬底的有源区相交而不在隔离区上形成。 因此，可以避免来自相邻存储单元的不期望​​的影响或干扰。

公开(公告)号：US06750525B2

公开(公告)日：2004-06-15

申请号：US10099581

申请日：2002-03-15

申请人： Yong-Sik Yim ,  Jung-Dal Choi ,  Hong-Suk Kwack ,  You-Cheol Shin

发明人： Yong-Sik Yim ,  Jung-Dal Choi ,  Hong-Suk Kwack ,  You-Cheol Shin

IPC分类号： H01L2900

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L29/792

摘要： A non-volatile memory device having a MONOS (Metal-oxide-nitride-oxide-semiconductor) gate structure is provided. This device includes a selection transistor and a cell transistor including a cell gate insulation layer formed in a cell array area and a low-voltage MOS transistor having a low-voltage gate insulation layer and a high-voltage MOS transistor having a high-voltage gate insulation layer formed in a peripheral circuit area. The low-voltage gate insulation layer is thinner than the high-voltage gate insulation layer. The low-voltage gate insulation layer can also be thinner than the equivalent thickness of the cell gate insulation layer.

摘要翻译： 提供具有MONOS（金属氧化物 - 氮化物 - 氧化物半导体）栅极结构的非易失性存储器件。 该器件包括选择晶体管和包括形成在单元阵列区域中的单元栅极绝缘层和具有低压栅极绝缘层的低压MOS晶体管和具有高压栅极的高压MOS晶体管的单元晶体管 绝缘层形成在外围电路区域中。 低压栅极绝缘层比高压栅极绝缘层薄。 低压栅极绝缘层也可以比单元栅极绝缘层的等效厚度薄。

公开(公告)号：US06734065B2

公开(公告)日：2004-05-11

申请号：US10418848

申请日：2003-04-18

申请人： Yong-Sik Yim ,  Jung-Dal Choi ,  Hong-Suk Kwack ,  You-Cheol Shin

发明人： Yong-Sik Yim ,  Jung-Dal Choi ,  Hong-Suk Kwack ,  You-Cheol Shin

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L29/792

摘要： Embodiments of the invention provide a method that includes forming a selection transistor and a cell transistor that includes a cell gate insulation layer in a cell array area. The method also includes forming a low-voltage MOS transistor having a low-voltage gate insulation layer and a high-voltage MOS transistor having a high-voltage gate insulation layer in a peripheral circuit area. The low-voltage gate insulation layer is formed thinner than the high-voltage gate insulation layer. The low voltage gate insulation layer may also be formed thinner than the equivalent thickness of the cell gate insulation layer.

摘要翻译： 本发明的实施例提供了一种方法，其包括在单元阵列区域中形成选择晶体管和包括单元栅极绝缘层的单元晶体管。 该方法还包括在外围电路区域中形成具有低电压栅极绝缘层的低压MOS晶体管和具有高电压栅极绝缘层的高压MOS晶体管。 低压栅极绝缘层的形成比高压栅极绝缘层薄。 低压栅极绝缘层也可以形成为比单元栅极绝缘层的等效厚度更薄。