公开(公告)号：US08193845B2

公开(公告)日：2012-06-05

申请号：US12831208

申请日：2010-07-06

Applicant: Heng-Yu Jian ,  Zhiwei Xu ,  Yi-Cheng Wu ,  Mau-Chung Frank Chang

Inventor： Heng-Yu Jian ,  Zhiwei Xu ,  Yi-Cheng Wu ,  Mau-Chung Frank Chang

IPC: H03L7/06

CPC classification number: H03L7/1976

Abstract: A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.

Abstract translation: 锁相环包括量化电路，其从Δ-Σ调制器中的误差产生异相噪声消除信号，并将噪声消除信号施加到电荷泵。 量化电路包括数模转换微分器。 数/模微分器可以是例如单位一阶数模比较器，单位二阶数模比较器或全M位二进制加权 数字到模拟微分器。

公开(公告)号：US07860470B2

公开(公告)日：2010-12-28

申请号：US11781198

申请日：2007-07-20

Applicant: Zhiwei Xu ,  Heng-Yu Jian ,  Yi-Cheng Wu ,  Charles Chien

Inventor： Zhiwei Xu ,  Heng-Yu Jian ,  Yi-Cheng Wu ,  Charles Chien

IPC: H03J7/32

CPC classification number: H04B1/30 ,  H03F3/245 ,  H03F3/45183 ,  H03F3/45237 ,  H03F2203/45631 ,  H03F2203/45638

Abstract: A local oscillator (LO) buffer circuit comprises first and second LO buffers arranged in a cross coupled configuration. The first LO buffer generates in-phase output signals in response to in-phase input signals, and quadrature output signals from the second LO buffer. The second LO buffer generates the quadrature output signals in response to quadrature input signals and the in-phase output signals. The LO buffers may include inductive loads. The LO buffers may include MOS transistors or bipolar junction transistors.

Abstract translation: 本地振荡器（LO）缓冲电路包括以交叉耦合配置布置的第一和第二LO缓冲器。 第一LO缓冲器响应于同相输入信号和来自第二LO缓冲器的正交输出信号产生同相输出信号。 第二LO缓冲器响应于正交输入信号和同相输出信号产生正交输出信号。 LO缓冲器可以包括感性负载。 LO缓冲器可以包括MOS晶体管或双极结型晶体管。

公开(公告)号：US07609122B2

公开(公告)日：2009-10-27

申请号：US11868306

申请日：2007-10-05

Applicant: Heng-Yu Jian ,  Zhiwei Xu ,  Yi-Cheng Wu ,  Charles Chien

Inventor： Heng-Yu Jian ,  Zhiwei Xu ,  Yi-Cheng Wu ,  Charles Chien

IPC: H03B5/08

CPC classification number: H03L7/10 ,  H03L7/099

Abstract: A phase lock loop (PLL) includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the PLL. A capacitance profile for setting the frequency of the PLL at a process comer is stored. At power up, or after an idle time, a calibration is performed at two frequencies. The capacitances of operating the phase lock loop at the two frequencies are determined and stored. During a frequency change, the capacitance of operating the PLL is determined from the capacitance profile and stored capacitances. The capacitance of the PLL is presumed to change linearly with frequency and the two stored capacitances are used to determine a difference capacitance at the selected frequency by linear interpolating between the two stored capacitances, which is added to the capacitance in the capacitance profile at the selected frequency to generate an operating capacitance.

Abstract translation: 锁相环（PLL）包括用于通过制造包括PLL的集成电路的过程变化校准用于电容变化的振荡电路的校准回路。 存储用于在处理角设定PLL的频率的电容分布。 在上电或空闲时间后，以两个频率进行校准。 确定并存储在两个频率下操作锁相环的电容。 在频率变化期间，操作PLL的电容由电容曲线和存储的电容确定。 假设PLL的电容随频率线性变化，并且两个存储的电容用于通过在所选择的电容分布中的电容相加的两个存储的电容之间的线性内插来确定所选频率处的差电容， 产生一个工作电容的频率。

公开(公告)号：US20090023413A1

公开(公告)日：2009-01-22

申请号：US11781198

申请日：2007-07-20

Applicant: Zhiwei XU ,  Heng-Yu JIAN ,  Yi-Cheng WU ,  Charles CHIEN

Inventor： Zhiwei XU ,  Heng-Yu JIAN ,  Yi-Cheng WU ,  Charles CHIEN

IPC: H04B1/26

CPC classification number: H04B1/30 ,  H03F3/245 ,  H03F3/45183 ,  H03F3/45237 ,  H03F2203/45631 ,  H03F2203/45638

Abstract: A local oscillator (LO) buffer circuit comprises first and second LO buffers arranged in a cross coupled configuration. The first LO buffer generates in-phase output signals in response to in-phase input signals, and quadrature output signals from the second LO buffer. The second LO buffer generates the quadrature output signals in response to quadrature input signals and the in-phase output signals. The LO buffers may include inductive loads. The LO buffers may include MOS transistors or bipolar junction transistors.

Abstract translation: 本地振荡器（LO）缓冲电路包括以交叉耦合配置布置的第一和第二LO缓冲器。 第一LO缓冲器响应于同相输入信号和来自第二LO缓冲器的正交输出信号产生同相输出信号。 第二LO缓冲器响应于正交输入信号和同相输出信号产生正交输出信号。 LO缓冲器可以包括感性负载。 LO缓冲器可以包括MOS晶体管或双极结型晶体管。

公开(公告)号：US20050103404A1

公开(公告)日：2005-05-19

申请号：US10993674

申请日：2004-11-19

Applicant: Meng-Hsin Hsieh ,  Yi-Cheng Wu ,  Pei-Te Huang ,  Hao-Shang Liu

Inventor： Meng-Hsin Hsieh ,  Yi-Cheng Wu ,  Pei-Te Huang ,  Hao-Shang Liu

IPC: C22C38/42

CPC classification number: C22C38/42 ,  C22C38/001 ,  C22C38/02 ,  C22C38/58

Abstract: An austenitic stainless steel includes (a) 0.03 wt % to 0.12 wt % of C, (b) 0.2 wt % to 1.0 wt % of Si, (c) 7.5 wt % to 10.5 wt % of Mn, (d) 14.0 wt % to 16.0 wt % of Cr, (e) 4.05 wt % to 4.31 wt % of Ni, (f) 0.04 wt % to 0.07 wt % of N, (g) 1.0 wt % to 3.5 wt % of Cu, (h) trace amount of Mo, and the balance being Fe and incidental impurities. The austenitic stainless steel has a δ-ferrite content less than 8.5 and equal to 6.77[(d)+(h)+1.5(b)]−4.85[(e)+30(a)+30(f)+0.5(c)+0.3(g)]−52.75.

Abstract translation: 奥氏体不锈钢包括（a）0.03重量％至0.12重量％的C，（b）0.2重量％至1.0重量％的Si，（c）7.5重量％至10.5重量％的Mn，（d）14.0重量％ 至6.0重量％的Cr，（e）4.05重量％至4.31重量％的Ni，（f）0.04重量％至0.07重量％的N，（g）1.0重量％至3.5重量％的Cu，（h）痕量 Mo量，余量为Fe和杂质。 奥氏体不锈钢的δ-铁素体含量小于8.5，等于6.77 [（d）+（h）+1.5（b）] - 4.85 [（e）+30（a）+30（f）+0.5（ c）+0.3（g）] - 52.75。

公开(公告)号：US07780908B2

公开(公告)日：2010-08-24

申请号：US11866869

申请日：2007-10-03

Applicant: Meng-Hsin Hsieh ,  Yi-Cheng Wu ,  Pei-Te Huang ,  Hao-Shang Liu

Inventor： Meng-Hsin Hsieh ,  Yi-Cheng Wu ,  Pei-Te Huang ,  Hao-Shang Liu

IPC: C22C38/58

CPC classification number: C22C38/42 ,  C22C38/001 ,  C22C38/02 ,  C22C38/58

Abstract: An austenitic stainless steel includes (a) 0.03 wt % to 0.12 wt % of C, (b) 0.2 wt % to 1.0 wt % of Si, (c) 8.55 wt % to 10.12 wt % of Mn, (d) 14.0 wt % to 16.0 wt % of Cr, (e) 4.05 wt % to 4.31 wt % of Ni, (f) 0.04 wt % to 0.07 wt % of N, (g) 1.0 wt % to 3.5 wt % of Cu, (h) trace amount of Mo, and the balance being Fe and incidental impurities. The austenitic stainless steel has a δ-ferrite content less than 8.5 and equal to 6.77[(d)+(h)+1.5(b)]−4.85[(e)+30(a)+30(f)+0.5(c)+0.3(g)]−52.75.

Abstract translation: 奥氏体不锈钢包括（a）0.03重量％至0.12重量％的C，（b）0.2重量％至1.0重量％的Si，（c）8.55重量％至10.12重量％的Mn，（d）14.0重量％ 至6.0重量％的Cr，（e）4.05重量％至4.31重量％的Ni，（f）0.04重量％至0.07重量％的N，（g）1.0重量％至3.5重量％的Cu，（h）痕量 Mo量，余量为Fe和杂质。 奥氏体不锈钢的δ-铁素体含量小于8.5，等于6.77 [（d）+（h）+1.5（b）] - 4.85 [（e）+30（a）+30（f）+0.5（ c）+0.3（g）] - 52.75。

公开(公告)号：US20080075623A1

公开(公告)日：2008-03-27

申请号：US11866869

申请日：2007-10-03

Applicant: Meng-Hsin Hsieh ,  Yi-Cheng Wu ,  Pei-Te Huang ,  Hao-Shang Liu

Inventor： Meng-Hsin Hsieh ,  Yi-Cheng Wu ,  Pei-Te Huang ,  Hao-Shang Liu

IPC: C22C38/58

CPC classification number: C22C38/42 ,  C22C38/001 ,  C22C38/02 ,  C22C38/58

Abstract: An austenitic stainless steel includes (a) 0.03 wt % to 0.12 wt % of C, (b) 0.2 wt % to 1.0 wt % of Si, (c) 8.55 wt % to 10.12 wt % of Mn, (d) 14.0 wt % to 16.0 wt % of Cr, (e) 4.05 wt % to 4.31 wt % of Ni, (f) 0.04 wt % to 0.07 wt % of N, (g) 1.0 wt % to 3.5 wt % of Cu, (h) trace amount of Mo, and the balance being Fe and incidental impurities. The austenitic stainless steel has a δ-ferrite content less than 8.5 and equal to 6.77[(d)+(h)+1.5(b)]−4.85[(e)+30(a)+30(f)+0.5(c)+0.3(g)]−52.75.

Abstract translation: 奥氏体不锈钢包括（a）0.03重量％至0.12重量％的C，（b）0.2重量％至1.0重量％的Si，（c）8.55重量％至10.12重量％的Mn，（d）14.0重量％ 至6.0重量％的Cr，（e）4.05重量％至4.31重量％的Ni，（f）0.04重量％至0.07重量％的N，（g）1.0重量％至3.5重量％的Cu，（h）痕量 Mo量，余量为Fe和杂质。 奥氏体不锈钢的δ-铁素体含量小于8.5，等于6.77 [（d）+（h）+1.5（b）] - 4.85 [（e）+30（a）+30（f）+0.5（ c）+0.3（g）] - 52.75。

公开(公告)号：US20130050034A1

公开(公告)日：2013-02-28

申请号：US13253975

申请日：2011-10-06

Applicant: Yi-Cheng Wu ,  Yi-Jie Wang ,  Chao-Chun Lin ,  Cheng-Hsiung Hsu ,  I-Shan Chen ,  Ta-Wei Hsu

Inventor： Yi-Cheng Wu ,  Yi-Jie Wang ,  Chao-Chun Lin ,  Cheng-Hsiung Hsu ,  I-Shan Chen ,  Ta-Wei Hsu

IPC: H01Q1/32 ,  H01Q1/42

CPC classification number: H01Q1/3233 ,  H01Q1/42

Abstract: An automotive radar device and an antenna cover are disclosed. The automotive radar device includes a base, an antenna disposed on the base, and the antenna cover. The antenna cover includes a main portion and an engagement portion connected to the circumference of the main portion. The engagement portion can be engaged to the base such that the main portion covers the antenna. Therein, a thickness of the main portion along a radiation direction of the antenna is equal to half-wavelength corresponding to a center operation frequency of the antenna under a dielectric constant of the main portion. Thereby, energy radiated from the antenna can mostly pass through the main portion without excessive signal attenuation, which solves the insufficient signal intensity due to a protection cover in the prior art. Further, the main portion can be made of flexible and weather resistant material to improve its physical and chemical properties.

Abstract translation: 公开了一种汽车雷达装置和天线罩。 汽车雷达装置包括基座，设置在基座上的天线和天线盖。 天线罩包括主体部分和与主体部分的圆周连接的接合部分。 接合部分可以接合到基座，使得主要部分覆盖天线。 其中，沿着天线的辐射方向的主要部分的厚度等于在主要部分的介电常数下对应于天线的中心操作频率的半波长。 因此，从天线辐射的能量可以大部分通过主要部分而没有过多的信号衰减，这解决了现有技术中由于保护罩引起的信号强度不足。 此外，主要部分可以由柔性和耐候性材料制成，以改善其物理和化学性质。

公开(公告)号：US20120007643A1

公开(公告)日：2012-01-12

申请号：US12831208

申请日：2010-07-06

Applicant: Heng-Yu Jian ,  Zhiwei Xu ,  Yi-Cheng Wu ,  Mau-Chung Frank Chang

Inventor： Heng-Yu Jian ,  Zhiwei Xu ,  Yi-Cheng Wu ,  Mau-Chung Frank Chang

IPC: H03L7/08

CPC classification number: H03L7/1976

Abstract: A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.

Abstract translation: 锁相环包括量化电路，其从Δ-Σ调制器中的误差产生异相噪声消除信号，并将噪声消除信号施加到电荷泵。 量化电路包括数模转换微分器。 数/模微分器可以是例如单位一阶数模比较器，单位二阶数模比较器或全M位二进制加权 数字到模拟微分器。

公开(公告)号：US07012472B2

公开(公告)日：2006-03-14

申请号：US10888861

申请日：2004-07-09

Applicant: Zhiwei Xu ,  Yi-Cheng Wu ,  Mau-Chung Frank Chang

Inventor： Zhiwei Xu ,  Yi-Cheng Wu ,  Mau-Chung Frank Chang

IPC: H03L7/00

CPC classification number: H03L5/00 ,  H03B5/04 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1278 ,  H03B5/1293

Abstract: A system or method for controlling a voltage controlled oscillator (VCO) or LO buffer includes an amplitude detector for detecting an amplitude value at a node corresponding to the at least one output line. A comparator compares the detected amplitude value with a predetermined amplitude value, and outputs a first digital value when the detected amplitude value is greater than the predetermined amplitude value, and a second digital value when the detected amplitude value is less than the predetermined amplitude value. An accumulator accumulates outputs of the comparator so as to provide an accumulated digital amplitude value. A digital-to-analog converter converts the accumulated digital amplitude value to an accumulated analog amplitude value. The analog accumulated amplitude value is provided as an updated bias control signal to the bias transistor of the VCO or LO buffer.

Abstract translation: 用于控制压控振荡器（VCO）或LO缓冲器的系统或方法包括：幅度检测器，用于检测与至少一条输出线对应的节点处的振幅值。 比较器将检测到的振幅值与预定的振幅值进行比较，当检测到的振幅值大于预定振幅值时，输出第一数字值，当检测到的振幅值小于预定振幅值时，输出第二数字值。 累加器累积比较器的输出，以提供累加的数字振幅值。 数模转换器将累积的数字振幅值转换为累积的模拟幅度值。 模拟累积振幅值作为更新的偏置控制信号提供给VCO或LO缓冲器的偏置晶体管。