公开(公告)号：US20120173942A1

公开(公告)日：2012-07-05

申请号：US12982409

申请日：2010-12-30

申请人： Chang-Ho Do ,  Yeon-Woo Kim ,  Bok-Moon Kang ,  Tae-Hyung Jung

发明人： Chang-Ho Do ,  Yeon-Woo Kim ,  Bok-Moon Kang ,  Tae-Hyung Jung

IPC分类号： G06F11/16

CPC分类号： G11C29/1201

摘要： A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells; a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads; a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells during a test mode; and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

摘要翻译： 半导体存储器件包括多个存储体，每个存储体包括多个第一存储单元和多个第二存储单元; 第一输入/输出单元，被配置为在第一存储器单元和多个第一数据焊盘之间传送第一数据; 第二输入/输出单元，被配置为在第二存储器单元和多个第二数据焊盘之间传送第二数据; 路径选择单元，被配置为在测试模式期间将通过第一数据焊盘输入的第一数据传送到第一和第二存储器单元; 以及测试模式控制单元，被配置为在测试模式期间比较第一和第二存储器单元的第一数据，并且基于比较结果来控制至少一个第一数据焊盘来表示故障状态。

公开(公告)号：US08713383B2

公开(公告)日：2014-04-29

申请号：US12982409

申请日：2010-12-30

申请人： Chang-Ho Do ,  Yeon-Woo Kim

发明人： Chang-Ho Do ,  Yeon-Woo Kim

IPC分类号： G01R31/28

CPC分类号： G11C29/1201

摘要： A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells; a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads; a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells during a test mode; and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

摘要翻译： 半导体存储器件包括多个存储体，每个存储体包括多个第一存储单元和多个第二存储单元; 第一输入/输出单元，被配置为在第一存储器单元和多个第一数据焊盘之间传送第一数据; 第二输入/输出单元，被配置为在第二存储器单元和多个第二数据焊盘之间传送第二数据; 路径选择单元，被配置为在测试模式期间将通过第一数据焊盘输入的第一数据传送到第一和第二存储器单元; 以及测试模式控制单元，被配置为在测试模式期间比较第一和第二存储器单元的第一数据，并且基于比较结果来控制至少一个第一数据焊盘来表示故障状态。

公开(公告)号：US08595575B2

公开(公告)日：2013-11-26

申请号：US12982423

申请日：2010-12-30

申请人： Chang-Ho Do ,  Bok-Moon Kang ,  Tae-Hyung Jung ,  Yeon-Woo Kim

发明人： Chang-Ho Do ,  Bok-Moon Kang ,  Tae-Hyung Jung ,  Yeon-Woo Kim

IPC分类号： G01R31/28

CPC分类号： G11C29/1201 ,  G11C29/40

摘要： A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads, a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control the first data pads to denote a fail status based on a comparison result, during the test mode.

摘要翻译： 半导体存储器件包括多个存储体，每个存储体包括多个第一存储器单元和多个第二存储器单元，第一输入/输出单元，被配置为在第一存储单元和多个第一数据焊盘之间传送第一数据， 第二输入/输出单元，被配置为在第二存储器单元和多个第二数据焊盘之间传送第二数据;路径选择单元，被配置为将通过第一数据焊盘输入的第一数据传送到第一和第二存储器 以及测试模式控制单元，被配置为比较第一和第二存储器单元的第一数据，并且在测试模式期间，基于比较结果来控制第一数据焊盘来表示故障状态。

公开(公告)号：US20090151371A1

公开(公告)日：2009-06-18

申请号：US12089137

申请日：2006-09-06

申请人： Sang Joon Eum ,  Yun Hi Lee ,  Yeon Woo Kim ,  Seoung Min Kang ,  Jea Young Choi ,  Jeong Ho Lee ,  Bum Dong Sa ,  Chang Gyu Kim ,  Jae Hun Lee

发明人： Sang Joon Eum ,  Yun Hi Lee ,  Yeon Woo Kim ,  Seoung Min Kang ,  Jea Young Choi ,  Jeong Ho Lee ,  Bum Dong Sa ,  Chang Gyu Kim ,  Jae Hun Lee

IPC分类号： F25B49/00 ,  H02P1/42

CPC分类号： H02P1/445 ,  F04B49/06 ,  H02P25/04 ,  H02P25/18

摘要： The present invention relates to a compressor (5) and a refrigerator with the same, and more particularly, to a power saving type compressor which can prevent unnecessary consumption of a current for the compressor to have high energy efficiency, and a refrigerator with the same and a method for controlling the same, wherein the power saving type compressor includes a main winding and a sub-winding respectively having a main terminal (R) and a sub-terminal(s) main winding and a sub-winding being connected with a common terminal to each other, and a PTC switching unit between a PTC unit connected to the sub-terminal for increasing a starting torque in operation of the compressor and the main terminal, for making selective switching on/off of a power input to the PTC unit.

摘要翻译： 压缩机及其制冷机技术领域本发明涉及一种压缩机（5）及其制冷机，更具体地说，涉及能够防止不必要地消耗压缩机的电流而具有高能量效率的节能型压缩机，以及具有该压缩机的冰箱 及其控制方法，其中所述省电型压缩机包括分别具有主端子（R）和副端子主绕组的主绕组和次级绕组，以及与副端子 公共端子，以及连接到副端子的PTC单元之间的PTC切换单元，用于增加在压缩机和主端子的运行中的起动转矩，用于选择性地切换到输入到PTC的功率的接通/断开 单元。

公开(公告)号：US20120173937A1

公开(公告)日：2012-07-05

申请号：US12982607

申请日：2010-12-30

申请人： Chang-Ho DO ,  Yeon-Woo KIM

发明人： Chang-Ho DO ,  Yeon-Woo KIM

IPC分类号： G11C29/10 ,  G06F11/26

CPC分类号： G11C29/1201 ,  G11C29/48

摘要： A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

摘要翻译： 半导体存储器件包括多个存储体，每个存储体包括多个第一存储器单元和多个第二存储器单元，第一输入/输出单元，被配置为在第一存储器单元和多个第一数据焊盘之间传送第一数据; 第二输入/输出单元，被配置为在第二存储器单元和多个第二数据焊盘之间传送第二数据;路径选择单元，被配置为将通过第一数据焊盘输入的第一数据传送到第一和第二数据焊盘 以及测试模式控制单元，被配置为比较第一和第二存储器单元的第一数据，并且基于比较结果来控制至少一个第一数据焊盘来表示故障状态， 在测试模式下。