公开(公告)号：US20070190998A1

公开(公告)日：2007-08-16

申请号：US11442221

申请日：2006-05-30

Applicant: Masayuki Tanaka ,  Satoshi Tanaka ,  Yasuhiro Ooba

Inventor： Masayuki Tanaka ,  Satoshi Tanaka ,  Yasuhiro Ooba

IPC: H04Q7/20

CPC classification number: H04L67/2823 ,  H04L67/28 ,  H04L69/08

Abstract: A protocol converting unit stores identification information for identifying a transfer path for data in a second network and a transmission source address specified in a packet in a corresponding manner. A failure detecting unit detects a transfer path in which a failure has occurred in the second network. A dummy-packet transmitting unit obtains a transmission source address corresponding to identification information of the transfer path in which the failure is detected, and transmits a dummy packet in which the obtained transmission source address is specified as the transmission source address to a first network.

Abstract translation: 协议转换单元以相应的方式存储用于识别在第二网络中的数据的传送路径和分组中指定的传输源地址的标识信息。 故障检测单元检测在第二网络中发生故障的传送路径。 虚拟分组发送单元获得与检测到故障的传送路径的识别信息相对应的发送源地址，并将所获得的发送源地址被指定为发送源地址的虚拟分组发送到第一网络。

公开(公告)号：US07249216B2

公开(公告)日：2007-07-24

申请号：US11055330

申请日：2005-02-10

Applicant: Yuichi Uzawa ,  Yasuhiro Ooba

Inventor： Yuichi Uzawa ,  Yasuhiro Ooba

IPC: G06F12/00

CPC classification number: H04L45/7453 ,  G06F17/30982

Abstract: A data relay apparatus in which a search request command can be inputted efficiently to a content addressable/associative memory device. When a packet is inputted, a network processor generates a search request and passes it to the content addressable/associative memory device. Then the content addressable/associative memory device analyzes the structure of the search request and generates a plurality of search conditions. The content addressable/associative memory device makes a search according to each search condition and outputs a memory address corresponding to a detected piece of information to be searched to a memory device. The memory device passes a candidate search result corresponding to the memory address to the network processor as a search result.

Abstract translation: 一种数据中继装置，其中搜索请求命令可以有效地输入到内容寻址/关联存储装置。 当分组被输入时，网络处理器产生搜索请求并将其传递到内容寻址/关联存储设备。 然后内容可寻址/关联存储器件分析搜索请求的结构并产生多个搜索条件。 内容可寻址/关联存储器装置根据每个搜索条件进行搜索，并将与检测到的要搜索的信息相对应的存储器地址输出到存储器件。 存储器件将与存储器地址相对应的候选搜索结果作为搜索结果传递给网络处理器。

公开(公告)号：US06862621B2

公开(公告)日：2005-03-01

申请号：US09902843

申请日：2001-07-11

Applicant: Syuji Takada ,  Yasuhiro Ooba

Inventor： Syuji Takada ,  Yasuhiro Ooba

IPC: H04L12/813 ,  H04L12/823 ,  G06F15/173

CPC classification number: H04L49/90 ,  H04L47/10 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/32 ,  H04L47/50 ,  H04L47/522 ,  H04L47/54 ,  H04L47/6265 ,  H04L47/627 ,  H04L49/9078

Abstract: The invention relates to a flow controlling apparatus provided in a node of a packet routing network, the flow controlling apparatus performing a rate-based congestion control on packets supplied via an incoming line as well as buffer management. The invention also relates to a node apparatus that incorporates such a flow controlling apparatus. In the flow controlling apparatus and the node apparatus, a frequency at which individual packets belonging to the flows are to be discarded during the course of buffer management are kept, for each flow, at approximately the same value. Therefore, in a network to which the invention is applied, the transmission quality is kept uniform and the service quality is highly maintained while flexible adaptation is made to various service forms.

Abstract translation: 本发明涉及一种设置在分组路由网络的节点中的流控制装置，该流控制装置对经由输入线路提供的分组以及缓冲器管理执行基于速率的拥塞控制。 本发明还涉及一种结合了这种流量控制装置的节点装置。 在流控制装置和节点装置中，对于每个流程，在缓冲器管理过程中保持属于流的各个分组的频率大致相同的值。 因此，在应用本发明的网络中，传输质量保持一致，服务质量高度保持，同时灵活地适应各种服务形式。

公开(公告)号：US06850520B1

公开(公告)日：2005-02-01

申请号：US09409145

申请日：1999-09-30

Applicant: Shuji Takada ,  Yasuhiro Ooba

Inventor： Shuji Takada ,  Yasuhiro Ooba

IPC: H04Q3/00 ,  H04L12/24 ,  H04L12/26 ,  H04L12/28 ,  H04L12/70

CPC classification number: H04L12/5601 ,  H04L2012/5625 ,  H04L2012/5652

Abstract: An ATM layer cell processing apparatus is provided with a plurality of cell processing sections, including a plurality of OAM cell processors provided with respect to each of OAM cell types, a cell identifying section outputting cell type information by decoding header information of an arrived cell, an OAM identifying section outputting OAM identification information including OAM type information identified based on OAM cell information of a payload and the cell type information, where the cell identifying section and the OAM identifying section are provided in common with respect to the plurality of cell processing sections including the plurality of OAM cell processors, and a mechanism sending the OAM ell type information and cell data of the arrived cell to a cell processing section which is to process the arrived cell at a subsequent stage, based on the OAM identification information output from the OAM identification section.

Abstract translation: ATM层信元处理装置具有多个小区处理部，包括针对每个OAM小区类型提供的多个OAM小区处理部，小区识别部，通过对到达小区的头信息进行解码来输出小区类型信息， OAM识别部，其输出包括基于有效载荷的OAM小区信息识别的OAM类型信息的OAM识别信息以及小区识别部和OAM识别部相对于多个小区处理部共同设置的小区类型信息 包括多个OAM小区处理器，以及将到达小区的OAM类型信息和小区数据发送到在后续阶段处理到达小区的小区处理部分的机制，基于从 OAM识别部分。

公开(公告)号：US06771600B2

公开(公告)日：2004-08-03

申请号：US09759102

申请日：2001-01-12

Applicant: Kenichi Kawarai ,  Takeshi Terada ,  Yasutaka Ohno ,  Yasuhiro Ooba

Inventor： Kenichi Kawarai ,  Takeshi Terada ,  Yasutaka Ohno ,  Yasuhiro Ooba

IPC: H04L1228

CPC classification number: H04L47/10 ,  H04L12/5601 ,  H04L2012/5625 ,  H04L2012/565 ,  H04L2012/5679

Abstract: A packet insertion interval control system includes a counting unit (32), having a first bit field for managing an insertion interval of a management packet required to be cyclically inserted and a second bit field for specifying a logic path for forwarding the management packet, for executing such a counting operation as to periodically cycle the first bit field and the second bit field, and a control unit (31) for executing control for specifying, when a count value indicated by the first bit field of the counting unit is a predetermined value, the logic path for forwarding the management packet on the basis of a count value indicated by the second bit field of the counting unit, and for inserting the management packet into the specified logic path. With this architecture, it is feasible to restrain an increase in quantity of the hardware and flexibly correspond to changes in the number of connections (number of channels) and the cell insertion interval (packet insertion interval) per communication system.

Abstract translation: 数据包插入间隔控制系统包括计数单元（32），其具有用于管理需要循环插入的管理分组的插入间隔的第一比特字段和用于指定用于转发管理分组的逻辑路径的第二比特字段，用于 执行这样的计数操作以周期性地循环第一位字段和第二位字段;以及控制单元（31），用于执行用于指定当计数单元的第一位字段指示的计数值是预定值时的控制 用于基于由计数单元的第二位字段指示的计数值转发管理包的逻辑路径，并用于将管理包插入到指定的逻辑路径中。 利用这种架构，可以抑制硬件数量的增加，并且灵活地对应于每个通信系统的连接数（通道数）和单元插入间隔（分组插入间隔）的变化。

公开(公告)号：US06639819B2

公开(公告)日：2003-10-28

申请号：US10011373

申请日：2001-10-22

Applicant: Yuichi Uzawa ,  Yasuhiro Ooba

Inventor： Yuichi Uzawa ,  Yasuhiro Ooba

IPC: G11C1500

CPC classification number: G11C15/00

Abstract: An associative memory apparatus has such a structure as to reduce a load of an updating work and readily cope with an increase of the capacity. The associative memory apparatus outputs longest prefix match in only one searching operation, thereby shortening a processing time for the searching process. The apparatus comprises entry units, each of which includes a logical operating means outputting information about a bit length not masked in entry data when the entry data stored in its own entry unit coincides with bit data that is a key, and a search result outputting means outputting a search match information with respect to the search key only when the entry data stored in its own entry unit is entry data having the longest bit length not masked.

公开(公告)号：US07149184B2

公开(公告)日：2006-12-12

申请号：US09858611

申请日：2001-05-16

Applicant: Syuji Takada ,  Yasuhiro Ooba

Inventor： Syuji Takada ,  Yasuhiro Ooba

IPC: H04J1/16 ,  H04J3/14

CPC classification number: H04L47/36 ,  H04L25/0262 ,  H04L47/10 ,  H04L47/11 ,  H04L47/20 ,  H04L47/21 ,  H04L47/215 ,  H04L47/32

Abstract: A transmission rate monitoring apparatus capable of promptly detecting the average transmission rate of data transmitted on a transmission channel. Data is received on the transmission channel, and a desired average transmission rate is set with respect to a predetermined time period. The amount of data received is measured and data is accepted or discarded in accordance with the data amount measured within the predetermined time period and the average transmission rate.

Abstract translation: 一种能够及时检测在传输信道上发送的数据的平均传输速率的传输速率监视装置。 在传输信道上接收数据，并且相对于预定时间段设置期望的平均传输速率。 测量接收到的数据量，并根据在预定时间段内测量的数据量和平均传输速率接收或丢弃数据。

公开(公告)号：US07075938B1

公开(公告)日：2006-07-11

申请号：US09258442

申请日：1999-02-26

Applicant: Syuji Takada ,  Yasuhiro Ooba

Inventor： Syuji Takada ,  Yasuhiro Ooba

IPC: H04L12/28

CPC classification number: H04L49/901 ,  H04L49/103 ,  H04L49/108 ,  H04L49/90 ,  H04L49/9036

Abstract: A common buffer memory control apparatus controls a common buffer memory which is used to store message data items each of which is divided into a plurality of cells based on an asynchronous transfer mode. The common buffer memory control apparatus includes a free block management table for managing whether each of blocks into which the common buffer memory divided is free or used, a block selecting unit for selecting a block of the common buffer memory which is free with reference to the free block management table, and a cell writing control unit for controlling a write operation for cells of a single message data item so that the respective cells of the single message data item are written in the block, selected by the block selecting means, of the common buffer memory.

Abstract translation: 公共缓冲存储器控制装置控制公共缓冲存储器，其用于存储基于异步传输模式将消息数据项分为多个单元的消息数据项。 公共缓冲存储器控制装置包括一个空闲块管理表，用于管理被分配的公共缓冲存储器中的每个块是空闲还是使用的块;块选择单元，用于选择公共缓冲存储器的块， 空闲块管理表和单元写入控制单元，用于控制单个消息数据项的单元的写入操作，使得单个消息数据项的各个单元被写入由块选择装置选择的块中 公共缓冲存储器。

公开(公告)号：US06895473B2

公开(公告)日：2005-05-17

申请号：US10298973

申请日：2002-11-12

Applicant: Masao Nakano ,  Takeshi Toyoyama ,  Yasuhiro Ooba

Inventor： Masao Nakano ,  Takeshi Toyoyama ,  Yasuhiro Ooba

IPC: G06F15/167 ,  G06F15/173 ,  H04L12/70 ,  H04L12/937 ,  H04Q11/04 ,  G06F12/00

CPC classification number: H04Q11/0478 ,  H04L2012/5625

Abstract: A data control device capable of high-quality, high-efficiency control for speeding up data processing, thus permitting improvement of the throughput of a system. Attribute analyzing unit analyzes an attribute of data, and a main memory stores setting information of the data in a region corresponding to the attribute. A highway cache memory stores the data, and also receives and transmits the data on a highway. A processor performs an operation on the data in accordance with the setting information. A data cache memory is interposed between the processor and the main memory and stores the setting information.

Abstract translation: 一种能够进行高质量，高效率控制的数据控制装置，用于加速数据处理，从而可以提高系统的吞吐量。 属性分析单元分析数据的属性，并且主存储器将数据的设置信息存储在与属性相对应的区域中。 公路缓存存储器存储数据，并且还在高速公路上接收和发送数据。 处理器根据设置信息对数据进行操作。 在处理器和主存储器之间插入数据高速缓冲存储器并存储设置信息。

公开(公告)号：US06633961B2

公开(公告)日：2003-10-14

申请号：US10067453

申请日：2002-02-05

Applicant: Syuji Takada ,  Yasuhiro Ooba

Inventor： Syuji Takada ,  Yasuhiro Ooba

IPC: G06F1200

CPC classification number: H04L12/5601 ,  H04L47/50 ,  H04L47/56 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9094 ,  H04L2012/5625 ,  H04L2012/5651 ,  H04L2012/5652 ,  H04L2012/5681 ,  H04Q11/0478

Abstract: In data insertion control technique; a plurality of buffers hold different types of data, which are to be inserted into a predetermined transmission medium and are equal in insertion priority, and a data insertion controller controls the data insertion order in which the data are to be inserted into the transmission medium by controlling the read process order in which the different types of data are to read from the buffers, based on the write process order in which the different types of data have been stored in the buffers. The result is that it is possible to realize exact data insertion in a minimum delay time.

Abstract translation: 数据插入控制技术; 多个缓冲器保存要插入到预定传输介质中并且插入优先级相等的不同类型的数据，并且数据插入控制器通过以下方式控制数据插入顺序，其中数据将被插入到传输介质中 基于不同类型的数据已经存储在缓冲器中的写入处理顺序来控制从缓冲器读取不同类型的数据的读取处理顺序。 结果是可以在最小延迟时间内实现准确的数据插入。