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公开(公告)号：US07973566B2
公开(公告)日：2011-07-05
申请号：US12952784
申请日：2010-11-23
IPC分类号： H03K19/20
CPC分类号： H03K19/20
摘要： A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value.
摘要翻译： 逻辑门实现逻辑表达式。 至少一个逻辑门输入至少接收一个输入逻辑门信号和至少一个控制信号。 至少一个输出用于产生逻辑门输出信号。 非线性更新器作为动态可配置元件操作以产生由控制信号选择的多个不同的逻辑门。 非线性更新器包括非线性更新器输出。 非线性更新器被配置为向输入逻辑门信号施加非线性函数，以产生表示由输入逻辑门信号上的多个不同逻辑门之一实现的逻辑表达式的非线性更新器输出信号。 比较器包括比较器输入，其适于基于非线性输出信号与参考阈值的比较来接收用于产生逻辑门输出信号的参考阈值。
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公开(公告)号：US20110062986A1
公开(公告)日：2011-03-17
申请号：US12952784
申请日：2010-11-23
IPC分类号： H03K19/173
CPC分类号： H03K19/20
摘要： A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value.
摘要翻译： 逻辑门实现逻辑表达式。 至少一个逻辑门输入接收至少一个输入逻辑门信号和至少一个控制信号。 至少一个输出用于产生逻辑门输出信号。 非线性更新器作为动态可配置元件操作以产生由控制信号选择的多个不同的逻辑门。 非线性更新器包括非线性更新器输出。 非线性更新器被配置为向输入逻辑门信号施加非线性函数，以产生表示由输入逻辑门信号上的多个不同逻辑门之一实现的逻辑表达式的非线性更新器输出信号。 比较器包括比较器输入，其适于基于非线性输出信号与参考阈值的比较来接收用于产生逻辑门输出信号的参考阈值。
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3.发明授权Method and apparatus for a chaotic computing module using threshold reference signal implementation 有权使用阈值参考信号实现的混沌计算模块的方法和装置公开(公告)号：US07096437B2
公开(公告)日：2006-08-22
申请号：US10680271
申请日：2003-10-07
IPC分类号： G06F17/50
CPC分类号： G06N7/08
摘要： A dynamically configurable logic gate can include a controller configured to provide a first threshold reference signal; an adder configured to sum the first threshold reference signal and at least one input signal to generate a summed signal; a chaotic updater configured to apply a nonlinear function to the summed signal; and a subtractor configured to determine an output signal by taking a difference between a second threshold reference signal and the processed summed signal from the chaotic updater. The logic gate can operate as one of a plurality of different logic gates responsive to adjusting at least one of the threshold reference signals.
摘要翻译： 动态配置的逻辑门可以包括配置成提供第一阈值参考信号的控制器; 加法器，被配置为对所述第一阈值参考信号和至少一个输入信号求和以产生求和信号; 混沌更新器，被配置为对所述求和信号应用非线性函数; 以及减法器，被配置为通过取得第二阈值参考信号和来自混沌更新器的经处理的相加信号之间的差来确定输出信号。 响应于调整至少一个阈值参考信号，逻辑门可以作为多个不同的逻辑门之一来操作。
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公开(公告)号：US5447520A
公开(公告)日：1995-09-05
申请号：US219567
申请日：1994-03-29
CPC分类号： A61N1/3621 , A61N1/3702 , Y10S128/925
摘要： Electrical stimuli delivered to cardiac tissue at times determined from a chaos stabilizing algorithm, converts arrhythmia activity to periodic beating by an interbeat interval shortening action, utilizing real time calculation based on a system parameter experimentally determined from intervention by the electrical stimuli.
摘要翻译： 通过从混沌稳定算法确定的时间传递到心脏组织的电刺激，通过间隔间隔缩短动作将心律不齐活动转化为周期性跳动，利用基于由电刺激干预实验确定的系统参数的实时计算。
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公开(公告)号：US5342401A
公开(公告)日：1994-08-30
申请号：US930945
申请日：1992-08-19
CPC分类号： A61N1/3621 , A61N1/3702 , Y10S128/925
摘要： Electrical stimuli delivered to cardiac tissue at times determined from a chaos stabilizing algorithm, converts arrhythmia activity to periodic beating by an interbeat interval shortening action, utilizing real time calculation based on a system parameter experimentally determined from intervention by the electrical stimuli.
摘要翻译： 通过从混沌稳定算法确定的时间传递到心脏组织的电刺激，通过间隔间隔缩短作用将心律失常活动转化为周期性跳动，利用基于由电刺激干预实验确定的系统参数的实时计算。
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公开(公告)号：US07863937B2
公开(公告)日：2011-01-04
申请号：US12394991
申请日：2009-02-27
IPC分类号： H03K19/20
CPC分类号： H03K19/20
摘要： A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value.
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公开(公告)号：US08447407B2
公开(公告)日：2013-05-21
申请号：US12917321
申请日：2010-11-01
IPC分类号： A61N1/3605
CPC分类号： A61B5/0476 , A61B5/4094 , A61B2562/0209 , A61B2562/046
摘要： Neuronal excitation and inhibition of the brain is tracked in the hippocampal CA1 network during a latent period, wherein biomarkers are observed which include a sustained increase in the firing rate of the excitatory postsynaptic field activity, paired with a subsequent decrease in the firing rate of the inhibitory postsynaptic field activity; the mean amplitude profiles of both fEPSP and fEPSP field potential activity during the latent period have characteristic shapes; both excitatory and inhibitory CA1 field activity firing rates are observed to follow a circadian rhythm that drifts during epileptogenesis; the circadian rhythms described are in-phase in controls and anti-phase during epileptogenesis; and the fEPSP rate drifts from a circadian rhythm to a greater extent than the fEPSP rate. An additional biomarker is a change in a circadian rhythm of core body temperature. Therapeutic measures can include thermal, chemical, or electrical modulation, in an open or closed loop process.
摘要翻译： 神经元激发和脑的抑制在海马CA1网络中在潜伏期被跟踪，其中观察到生物标志物，其包括兴奋性突触后场活性的燃烧速率的持续增加，随后随后的 抑制性突触后野外活动; 潜伏期内fEPSP和fEPSP场电位活动的平均振幅分布具有特征形状; 观察到兴奋性和抑制性CA1场活性发射率都遵循癫痫发生期间漂移的昼夜节律; 描述的昼夜节律在癫痫发生期间在对照和抗相中是同相的; 并且fEPSP速率从昼夜节律偏离到比fEPSP率更大的程度。 另外一个生物标志物是核心体温的昼夜节律变化。 治疗措施可以包括在开放或闭环过程中的热，化学或电调制。
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公开(公告)号：US08250055B2
公开(公告)日：2012-08-21
申请号：US12517959
申请日：2007-12-05
IPC分类号： G06F9/455
CPC分类号： G06F17/30946
摘要： A dynamical search engine for searching a database is also provided. The dynamical search engine includes an array of nonlinear dynamical elements. The nonlinear dynamical element information items in a manner that confines the state of each element on a fixed point and uniquely encodes the information items. The dynamical search engine also includes a controller for controlling electrical signals supplied to elements of the array in a predetermined sequence. One supplied signal increases a state value of each element of the array by a quantity defining a search key that corresponds to a searched-for information item. A subsequently supplied signal updates the state value of each element of the array by performing a nonlinear folding of each state value based on a predetermined pivot.
摘要翻译： 还提供了用于搜索数据库的动态搜索引擎。 动态搜索引擎包括非线性动力元素阵列。 非线性动力学元素信息项以将每个元素的状态限制在固定点上并且对信息项进行唯一编码的方式。 动态搜索引擎还包括用于以预定顺序控制提供给阵列的元件的电信号的控制器。 一个提供的信号通过定义与搜索到的信息项对应的搜索关键字的数量来增加阵列的每个元素的状态值。 随后提供的信号通过基于预定的枢轴执行每个状态值的非线性折叠来更新阵列的每个元件的状态值。
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9.发明授权Reconfigurable and reliable logic circuit elements that exploit nonlinearity and noise 有权可重构和可靠的逻辑电路元件，利用非线性和噪声公开(公告)号：US07924059B2
公开(公告)日：2011-04-12
申请号：US12394749
申请日：2009-02-27
IPC分类号： H03K19/20
CPC分类号： H03K19/1733
摘要： A logic gate is adapted to implement logical expressions. The logic gate includes at least one input that is adapted to receive an input signal and at least one control signal. At least one of the input signal and the control signal is a noise signal. At least one output is adapted to produce an output signal. A nonlinear updater operates as a dynamically configurable element and produces multiple different logic gates as selected by the control signal based at least in part on the noise signal. The nonlinear updater is electrically coupled to the input and is also electrically coupled to the output. The nonlinear updates is configured to apply a nonlinear function to the input signal in response to the control signal to produce the output signal representing a logical expression being implemented by one of the multiple different logic gates on the input signal.
摘要翻译： 逻辑门适用于实现逻辑表达式。 逻辑门包括适于接收输入信号和至少一个控制信号的至少一个输入。 输入信号和控制信号中的至少一个是噪声信号。 至少一个输出适于产生输出信号。 非线性更新器作为动态可配置元件操作，并且至少部分地基于噪声信号产生由控制信号选择的多个不同的逻辑门。 非线性更新器电耦合到输入端并且还电耦合到输出端。 非线性更新被配置为响应于控制信号将非线性函数应用于输入信号，以产生表示由输入信号上的多个不同逻辑门之一实现的逻辑表达式的输出信号。
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10.发明申请RECONFIGURABLE AND RELIABLE LOGIC CIRCUIT ELEMENTS THAT EXPLOIT NONLINEARITY AND NOISE 有权可重用和可靠的逻辑电路元件，开发非线性和噪声公开(公告)号：US20100219862A1
公开(公告)日：2010-09-02
申请号：US12394749
申请日：2009-02-27
IPC分类号： H03K19/20
CPC分类号： H03K19/1733
摘要： A logic gate is adapted to implement logical expressions. The logic gate includes at least one input that is adapted to receive an input signal and at least one control signal. At least one of the input signal and the control signal is a noise signal. At least one output is adapted to produce an output signal. A nonlinear updater operates as a dynamically configurable element and produces multiple different logic gates as selected by the control signal based at least in part on the noise signal. The nonlinear updater is electrically coupled to the input and is also electrically coupled to the output. The nonlinear updates is configured to apply a nonlinear function to the input signal in response to the control signal to produce the output signal representing a logical expression being implemented by one of the multiple different logic gates on the input signal.
摘要翻译： 逻辑门适用于实现逻辑表达式。 逻辑门包括适于接收输入信号和至少一个控制信号的至少一个输入。 输入信号和控制信号中的至少一个是噪声信号。 至少一个输出适于产生输出信号。 非线性更新器作为动态可配置元件操作，并且至少部分地基于噪声信号产生由控制信号选择的多个不同的逻辑门。 非线性更新器电耦合到输入端并且还电耦合到输出端。 非线性更新被配置为响应于控制信号将非线性函数应用于输入信号，以产生表示由输入信号上的多个不同逻辑门之一实现的逻辑表达式的输出信号。
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