公开(公告)号：US3934157A

公开(公告)日：1976-01-20

申请号：US508081

申请日：1974-09-23

申请人： William Joshua Evans

发明人： William Joshua Evans

IPC分类号： H03K19/088 ,  H03K19/08 ,  H03K5/01

CPC分类号： H03K19/088

摘要： A logic gate circuit includes parallel drive of an output transistor and an inverter transistor by an input transistor. The inverter transistor then drives an active pull-up transistor which improves switching speed. The parallel drive of the invention allows the use of the active pull-up transistor without requiring a change in circuit voltage levels.

摘要翻译： 逻辑门电路包括输入晶体管的并联驱动和由输入晶体管构成的反相器晶体管。 逆变器晶体管然后驱动有源上拉晶体管，其提高了开关速度。 本发明的并联驱动器允许使用有源上拉晶体管，而不需要电路电压电平的变化。

公开(公告)号：US3978515A

公开(公告)日：1976-08-31

申请号：US565801

申请日：1975-04-07

申请人： William Joshua Evans ,  Wesley Norman Grant ,  Bernard Thomas Murphy

发明人： William Joshua Evans ,  Wesley Norman Grant ,  Bernard Thomas Murphy

IPC分类号： H01L21/00 ,  H01L21/285 ,  H01L23/522 ,  H01L27/00 ,  H01L27/02 ,  H01L27/082 ,  H01L29/06 ,  H01L29/08 ,  H01L27/04

CPC分类号： H01L29/0804 ,  H01L21/00 ,  H01L21/28525 ,  H01L23/522 ,  H01L27/00 ,  H01L27/0233 ,  H01L27/0821 ,  H01L29/0649 ,  H01L2924/0002 ,  Y10S148/122

摘要： An integrated injection logic circuit cell structure and its fabrication are simplified. A pattern of oxide isolation regions is used to define, at least partially, the introduction of two types of impurities in such a way as to reduce the number of masking steps. Certain of these oxide regions do not penetrate through the conventional epitaxial layer, leaving a lateral buried path to serve as the base of a lateral injection transistor. A pattern of polycrystalline silicon containing impurities is used both as a diffusion source and an interconnection.

公开(公告)号：US3962779A

公开(公告)日：1976-06-15

申请号：US535445

申请日：1974-12-23

申请人： Roger Edwards ,  William Joshua Evans ,  Wesley Norman Grant ,  Bernard Thomas Murphy

发明人： Roger Edwards ,  William Joshua Evans ,  Wesley Norman Grant ,  Bernard Thomas Murphy

IPC分类号： H01L21/762 ,  H01L23/522 ,  B01J17/00

CPC分类号： H01L21/76202 ,  H01L21/762 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S148/02 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/116 ,  Y10S148/117 ,  Y10S438/98

摘要： A method of making an oxide isolated integrated circuit structure is simplified by forming a first level metallization pattern without the conventional underlying insulating layer and without the need for restricting the size of the metallization to the size of the semiconductor regions to be contacted. Portions of the first level metallization pattern can extend on the oxide isolation region to contact two otherwise isolated semiconductor zones. Additionally, subsequent to the formation of the oxide isolation regions and the first level metallization, an intermediate dielectric masking pattern is formed so the combination of the first level metallization, the oxide isolation regions and the masking pattern defines zones for the introduction of impurities. Further, the masking pattern alone is used to provide contact holes for a subsequently formed second level metallization pattern.

摘要翻译： 通过在没有传统的底层绝缘层的情况下形成第一级金属化图案并且不需要将金属化的尺寸限制为要接触的半导体区域的尺寸，简化了制造氧化物隔离集成电路结构的方法。 第一级金属化图案的部分可以在氧化物隔离区域上延伸以接触两个否则隔离的半导体区域。 此外，在形成氧化物隔离区域和第一级金属化之后，形成中间电介质掩模图案，因此第一层金属化，氧化物隔离区域和掩模图案的组合限定用于引入杂质的区域。 此外，仅使用掩模图案来为随后形成的第二层金属化图案提供接触孔。