公开(公告)号：US07977774B2

公开(公告)日：2011-07-12

申请号：US11775566

申请日：2007-07-10

申请人： YeonHo Choi ,  GiJeong Kim ,  WanJong Kim

发明人： YeonHo Choi ,  GiJeong Kim ,  WanJong Kim

IPC分类号： H01L23/495

CPC分类号： H01L23/49551 ,  H01L23/49503 ,  H01L23/49541 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.

摘要翻译： 一种半导体封装，其包括限定多个外围边缘段的大致平坦的管芯焊盘和分离成至少两个同心的行的多个引线。 连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到每行的至少一些引线。 芯片，引线和半导体管芯的至少一部分被封装体封装，裸片焊盘的底表面和至少一排的引线暴露在封装主体的公共外表面中。

公开(公告)号：US20090014851A1

公开(公告)日：2009-01-15

申请号：US11775566

申请日：2007-07-10

申请人： YeonHo Choi ,  GiJeong Kim ,  WanJong Kim

发明人： YeonHo Choi ,  GiJeong Kim ,  WanJong Kim

IPC分类号： H01L23/495

CPC分类号： H01L23/49551 ,  H01L23/49503 ,  H01L23/49541 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.

摘要翻译： 一种半导体封装，其包括限定多个外围边缘段的大致平坦的管芯焊盘和分离成至少两个同心的行的多个引线。 连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到每行的至少一些引线。 芯片，引线和半导体管芯的至少一部分被封装体封装，裸片焊盘的底表面和至少一排的引线暴露在封装主体的公共外表面中。

公开(公告)号：US07847392B1

公开(公告)日：2010-12-07

申请号：US12242603

申请日：2008-09-30

申请人： Yeon Ho Choi ,  GiJeong Kim ,  WanJong Kim

发明人： Yeon Ho Choi ,  GiJeong Kim ,  WanJong Kim

IPC分类号： H01L23/49

CPC分类号： H01L23/49551 ,  H01L23/49548 ,  H01L23/49558 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least one row or ring which at least partially circumvents the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die paddle and some of the leads being exposed in a common exterior surface of the package body.

摘要翻译： 根据本发明，提供了包括唯一配置的引线框的半导体封装（例如，QFP封装），其尺寸和配置为使半导体封装中的暴露引线的可用数量最大化。 更具体地，本发明的半导体封装包括限定多个周边边缘段的大致平面的管芯焊盘或管芯焊盘。 此外，半导体封装包括多个引线。 这些引线中的一些包括暴露的底表面部分，其设置在至少一行或多个环中，该至少一行或多个环至少部分地绕开管芯焊盘，其他引线包括从半导体封装的封装主体的相应侧表面突出的部分。 连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到至少一些引线。 芯片焊盘，引线和半导体管芯的至少一部分被封装主体封装，其中裸片焊盘的底表面的至少部分和一些引线暴露在封装主体的公共外表面中 。

公开(公告)号：US08299602B1

公开(公告)日：2012-10-30

申请号：US12912490

申请日：2010-10-26

申请人： Yeon Ho Choi ,  GiJeong Kim ,  WanJong Kim

发明人： Yeon Ho Choi ,  GiJeong Kim ,  WanJong Kim

IPC分类号： H01L23/49

CPC分类号： H01L23/49551 ,  H01L23/49548 ,  H01L23/49558 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least one row or ring which at least partially circumvents the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die paddle and some of the leads being exposed in a common exterior surface of the package body.

摘要翻译： 根据本发明，提供了包括唯一配置的引线框的半导体封装（例如，QFP封装），其尺寸和配置为使半导体封装中的暴露引线的可用数量最大化。 更具体地，本发明的半导体封装包括限定多个周边边缘段的大致平面的管芯焊盘或管芯焊盘。 此外，半导体封装包括多个引线。 这些引线中的一些包括暴露的底表面部分，其设置在至少一行或多个环中，该至少一行或多个环至少部分地绕开管芯焊盘，其他引线包括从半导体封装的封装主体的相应侧表面突出的部分。 连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到至少一些引线。 芯片焊盘，引线和半导体管芯的至少一部分被封装主体封装，其中裸片焊盘的底表面的至少部分和一些引线暴露在封装主体的公共外表面中 。

公开(公告)号：US08304866B1

公开(公告)日：2012-11-06

申请号：US13151571

申请日：2011-06-02

申请人： YeonHo Choi ,  GiJeong Kim ,  WanJong Kim

发明人： YeonHo Choi ,  GiJeong Kim ,  WanJong Kim

IPC分类号： H01L23/495

CPC分类号： H01L23/49551 ,  H01L23/49503 ,  H01L23/49541 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.

摘要翻译： 一种半导体封装，其包括限定多个外围边缘段的大致平坦的管芯焊盘和分离成至少两个同心的行的多个引线。 连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到每行的至少一些引线。 芯片，引线和半导体管芯的至少一部分被封装体封装，裸片焊盘的底表面和至少一排的引线暴露在封装主体的公共外表面中。