公开(公告)号：US08839210B2

公开(公告)日：2014-09-16

申请号：US12382753

申请日：2009-03-23

Applicant: Teruhiko Kamigata ,  Atsuhiro Suga ,  Shigeru Kimura

Inventor： Teruhiko Kamigata ,  Atsuhiro Suga ,  Shigeru Kimura

IPC: G06F9/44 ,  G06F11/00 ,  G06F9/45

CPC classification number: G06F11/3612 ,  G06F11/3428 ,  G06F2201/865

Abstract: To provide a program performance analysis apparatus that can present to a user whether tuning made to a program operating on a predetermined hardware is either good or bad, a performance information acquisition unit for obtaining the performance information of a program, a difference information generation unit for generating difference information by making a comparison between the performance information of a first program and that of a second program obtained by making a change to the first program, and a change evaluation unit for evaluating whether the change is either good or bad are comprised.

Abstract translation: 为了提供一种程序性能分析装置，其可以向用户呈现无论对在预定硬件上操作的程序的调谐是好还是坏，执行信息获取单元用于获得程序的性能信息，差异信息生成单元，用于 通过对第一程序的性能信息和通过对第一程序进行改变而获得的第二程序的性能信息进行比较来生成差异信息，以及用于评估变化是好还是坏的变化评估单元。

公开(公告)号：US08732441B2

公开(公告)日：2014-05-20

申请号：US12558967

申请日：2009-09-14

Applicant: Teruhiko Kamigata

Inventor： Teruhiko Kamigata

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC classification number: G06F9/46 ,  G06F9/445

Abstract: A multiprocessing system includes a storage part that stores to a memory, a first operating system (OS) task set that is constituted by a combination of a first task and a first OS corresponding to the first task, the first task being designated by an execution instruction; and a task executing part that refers to the first OS task set stored to the memory, loads the OS constituting the first OS task set, and executes the first task designated by the execution instruction.

Abstract translation: 多处理系统包括存储部件，其存储到由第一任务和与第一任务相对应的第一OS的组合构成的第一操作系统（OS）任务集，第一任务由执行指定 指令; 以及参考存储到存储器中的第一OS任务集的任务执行部，加载构成第一OS任务集的OS，并执行由执行指令指定的第一任务。

公开(公告)号：US06868472B1

公开(公告)日：2005-03-15

申请号：US09671117

申请日：2000-09-28

Applicant: Hideo Miyake ,  Atsuhiro Suga ,  Yasuki Nakamura ,  Teruhiko Kamigata ,  Hitoshi Yoda ,  Hiroshi Okano ,  Yoshio Hirose

Inventor： Hideo Miyake ,  Atsuhiro Suga ,  Yasuki Nakamura ,  Teruhiko Kamigata ,  Hitoshi Yoda ,  Hiroshi Okano ,  Yoshio Hirose

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/00

CPC classification number: G06F12/0802 ,  G06F2212/2515

Abstract: In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.

Abstract translation: 在本发明的高速缓冲存储器控制方法和计算机中，高速缓存存储器连接到主存储器并被分成多个高速缓存块，并且锁定/解锁信号被提供给高速缓冲存储器以设置替换抑制 禁止将至少一个高速缓存块替换为主存储器的至少一个缓存块的状态，或者重置至少一个高速缓冲存储器时钟的替换禁止状态，使得更换高速缓存中的至少一个 阻塞到主内存是允许的。 通过使用高速缓冲存储器的其余高速缓冲存储器（除了至少一个高速缓存块之外）来执行读取或写入主存储器，使得当通过锁定/解锁信号设置替换禁止状态时， 在主存储器的读取或写入期间禁止将至少一个缓存块替换到主存储器。

公开(公告)号：US20060143416A1

公开(公告)日：2006-06-29

申请号：US11113056

申请日：2005-04-25

Applicant: Teruhiko Kamigata ,  Shinichiro Tago ,  Atsushi Ike ,  Yoshimasa Takebe

Inventor： Teruhiko Kamigata ,  Shinichiro Tago ,  Atsushi Ike ,  Yoshimasa Takebe

IPC: G06F12/14

CPC classification number: G06F9/526

Abstract: A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and an exclusive control unit coupled to the plurality of processors and configured to include a lock flag indicative of a locked/unlocked state regarding exclusive use of the resource, wherein the processors include a special purpose register interface coupled to the exclusive control unit, and are configured to access the lock flag by special purpose register access through the special purpose register interface.

Abstract translation: 多处理器系统包括多个处理器，耦合到多个处理器的共享总线，耦合到共享总线并被多个处理器共享的资源，以及耦合到多个处理器的排他控制单元，并且被配置为包括 指示关于资源的独占使用的锁定/解锁状态的锁定标志，其中处理器包括耦合到排他控制单元的专用寄存器接口，并且被配置为通过专用寄存器访问专用寄存器访问锁定标志 接口。

公开(公告)号：US20100005275A1

公开(公告)日：2010-01-07

申请号：US12558967

申请日：2009-09-14

Applicant: Teruhiko Kamigata

Inventor： Teruhiko Kamigata

IPC: G06F9/24

CPC classification number: G06F9/46 ,  G06F9/445

Abstract: A multiprocessing system includes a storage part that stores to a memory, a first operating system (OS) task set that is constituted by a combination of a first task and a first OS corresponding to the first task, the first task being designated by an execution instruction; and a task executing part that refers to the first OS task set stored to the memory, loads the OS constituting the first OS task set, and executes the first task designated by the execution instruction.

Abstract translation: 多处理系统包括存储部件，其存储到由第一任务和与第一任务相对应的第一OS的组合构成的第一操作系统（OS）任务集，第一任务由执行指定 指令; 以及参考存储到存储器中的第一OS任务集的任务执行部，加载构成第一OS任务集的OS，并执行由执行指令指定的第一任务。

公开(公告)号：US20090217247A1

公开(公告)日：2009-08-27

申请号：US12382753

申请日：2009-03-23

Applicant: Teruhiko Kamigata ,  Atsuhiro Suga ,  Shigeru Kimura

Inventor： Teruhiko Kamigata ,  Atsuhiro Suga ,  Shigeru Kimura

IPC: G06F9/44

CPC classification number: G06F11/3612 ,  G06F11/3428 ,  G06F2201/865

Abstract: To provide a program performance analysis apparatus that can present to a user whether tuning made to a program operating on a predetermined hardware is either good or bad, a performance information acquisition unit for obtaining the performance information of a program, a difference information generation unit for generating difference information by making a comparison between the performance information of a first program and that of a second program obtained by making a change to the first program, and a change evaluation unit for evaluating whether the change is either good or bad are comprised.

Abstract translation: 为了提供一种程序性能分析装置，其可以向用户呈现无论对在预定硬件上操作的程序的调谐是好还是坏，执行信息获取单元用于获得程序的性能信息，差异信息生成单元，用于 通过对第一程序的性能信息和通过对第一程序进行改变而获得的第二程序的性能信息进行比较来生成差异信息，以及用于评估变化是好还是坏的变化评估单元。

公开(公告)号：US07409506B2

公开(公告)日：2008-08-05

申请号：US11113056

申请日：2005-04-25

Applicant: Teruhiko Kamigata ,  Shinichiro Tago ,  Atsushi Ike ,  Yoshimasa Takebe

Inventor： Teruhiko Kamigata ,  Shinichiro Tago ,  Atsushi Ike ,  Yoshimasa Takebe

IPC: G06F13/18 ,  G06F13/16

CPC classification number: G06F9/526

Abstract: A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and an exclusive control unit coupled to the plurality of processors and configured to include a lock flag indicative of a locked/unlocked state regarding exclusive use of the resource, wherein the processors include a special purpose register interface coupled to the exclusive control unit, and are configured to access the lock flag by special purpose register access through the special purpose register interface.

Abstract translation: 多处理器系统包括多个处理器，耦合到多个处理器的共享总线，耦合到共享总线并被多个处理器共享的资源，以及耦合到多个处理器的排他控制单元，并且被配置为包括 指示关于资源的独占使用的锁定/解锁状态的锁定标志，其中处理器包括耦合到排他控制单元的专用寄存器接口，并且被配置为通过专用寄存器访问专用寄存器访问锁定标志 接口。

公开(公告)号：US07647473B2

公开(公告)日：2010-01-12

申请号：US10053707

申请日：2002-01-24

Applicant: Teruhiko Kamigata ,  Hideo Miyake

Inventor： Teruhiko Kamigata ,  Hideo Miyake

IPC: G06F15/00 ,  G06F9/45

CPC classification number: G06F8/447 ,  G06F9/3885

Abstract: An instruction processing method for checking an arrangement of basic instructions in a very long instruction word (VLIW) instruction, suitable for language processing systems, an assembler and a compiler, used for processors which execute variable length VLIW instructions designed based on variable length VLIW architecture.

Abstract translation: 一种用于检查适用于执行基于可变长度VLIW架构设计的可变长度VLIW指令的处理器的语言处理系统，汇编器和编译器的非常长的指令字（VLIW）指令中的基本指令的布置的指令处理方法 。

公开(公告)号：US20060224870A1

公开(公告)日：2006-10-05

申请号：US11444221

申请日：2006-05-31

Applicant: Shin-ichiro Tago ,  Taizo Sato ,  Yoshimasa Takebe ,  Yasuhiro Yamazaki ,  Teruhiko Kamigata ,  Atsuhiro Suga ,  Hiroshi Okano ,  Hitoshi Yoda

Inventor： Shin-ichiro Tago ,  Taizo Sato ,  Yoshimasa Takebe ,  Yasuhiro Yamazaki ,  Teruhiko Kamigata ,  Atsuhiro Suga ,  Hiroshi Okano ,  Hitoshi Yoda

IPC: G06F9/00

CPC classification number: G06F9/3804 ,  G06F9/3806 ,  G06F9/3846

Abstract: The present invention is defined in that an information processing device which reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing comprises: an instruction reading request portion which assigns a read address to the instruction store portion; an instruction buffering portion including a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion; a branching instruction detection portion which detects a branching instruction in the instruction sequence read from the instruction store portion; and a branch target address information buffering portion including a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction; wherein, when the branching instruction detection portion has detected a branching instruction, either the branch target address information of the branching instruction is stored in one of the plurality of branch target address information buffers, or the branch target instruction sequence of the branching instruction is stored in one of the plurality of instruction buffers in addition to the storing in the branch target address information buffer.

Abstract translation: 本发明的定义在于，通过流水线处理从指令存储部分读取，缓冲，解码和执行指令的信息处理设备包括：指令读取请求部分，其向指令存储部分分配读取地址; 指令缓冲部分，包括缓冲从指令存储部分读取的指令序列的多个指令缓冲器; 指令执行单元，其对由指令缓冲部分缓冲的指令进行解码和执行; 分支指令检测部分，其检测从指令存储部分读取的指令序列中的分支指令; 以及分支目标地址信息缓冲部分，包括多个分支目标地址信息缓冲器，当分支指令检测部分已经检测到分支指令时，缓冲用于生成分支指令的分支目标地址的转移目标地址信息; 其中，当分支指令检测部分已经检测到分支指令时，分支指令的分支目标地址信息被存储在多个分支目标地址信息缓冲器中的一个中，或分支指令的分支目标指令序列被存储 除了存储在分支目标地址信息缓冲器之外，还包括在多个指令缓冲器之一中。

公开(公告)号：US07134004B1

公开(公告)日：2006-11-07

申请号：US09666853

申请日：2000-09-20

Applicant: Shin-ichiro Tago ,  Taizo Sato ,  Yoshimasa Takebe ,  Yasuhiro Yamazaki ,  Teruhiko Kamigata ,  Atsuhiro Suga ,  Hiroshi Okano ,  Hitoshi Yoda

Inventor： Shin-ichiro Tago ,  Taizo Sato ,  Yoshimasa Takebe ,  Yasuhiro Yamazaki ,  Teruhiko Kamigata ,  Atsuhiro Suga ,  Hiroshi Okano ,  Hitoshi Yoda

IPC: G06F9/00

CPC classification number: G06F9/3804 ,  G06F9/3806 ,  G06F9/3846

Abstract: An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.

Abstract translation: 信息处理装置通过流水线处理从指令存储部分读取，缓冲，解码和执行指令，包括：向指令存储部分分配读取地址的指令读取请求部分，包括多个指令缓冲器的指令缓冲部分， 缓冲从指令存储部分读取的指令序列; 指令执行单元，其对由指令缓冲部分缓冲的指令进行解码和执行。 分支指令检测部分检测从指令存储部分读取的指令序列中的分支指令。 分支目标地址信息缓冲部分包括多个分支目标地址信息缓冲器，当分支指令检测部分已经检测到分支指令时，缓冲用于生成分支指令的分支目标地址的转移目标地址信息。