公开(公告)号：US20120070993A1

公开(公告)日：2012-03-22

申请号：US13303541

申请日：2011-11-23

Applicant: Scott R. Summerfelt ,  Ted S. Moise ,  Gul B. Basim

Inventor： Scott R. Summerfelt ,  Ted S. Moise ,  Gul B. Basim

IPC: H01L21/31

CPC classification number: H01L21/3185 ,  H01L21/0217 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5223 ,  H01L27/11509 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region.

Abstract translation: 一种用于形成覆盖铁电电容器和缓冲区域但是从逻辑区域的一部分去除的氢阻挡层的方法。

公开(公告)号：US20110079878A1

公开(公告)日：2011-04-07

申请号：US12890219

申请日：2010-09-24

Applicant: Rajni J. Aggarwal ,  Scott R. Summerfelt ,  Gul B. Basim ,  Ted S. Moise

Inventor： Rajni J. Aggarwal ,  Scott R. Summerfelt ,  Gul B. Basim ,  Ted S. Moise

IPC: H01L29/92 ,  H01L21/00

CPC classification number: H01L28/57 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

Abstract: An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer.

Abstract translation: 包含铁电电容器，下伏氢屏障和上覆氢阻挡层的集成电路。 一种用于形成包含铁电电容器，下伏氢屏障和上覆氢阻挡层的集成电路的方法。

公开(公告)号：US20110062550A1

公开(公告)日：2011-03-17

申请号：US12718691

申请日：2010-03-05

Applicant: Kezhakkedath R. Udayakumar ,  Scott R. Summerfelt ,  Ted S. Moise ,  Manoj K. Jain

Inventor： Kezhakkedath R. Udayakumar ,  Scott R. Summerfelt ,  Ted S. Moise ,  Manoj K. Jain

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L21/76843 ,  H01L27/11509 ,  H01L28/57

Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.

Abstract translation: 包含FeCap阵列的集成电路。 FeCap阵列在侧面至少部分地被氢阻挡壁包围，并且在顶部被氢阻挡顶板包围。 一种用于至少部分地封闭具有氢阻挡壁和氢阻挡顶板的FeCap阵列的方法。

公开(公告)号：US07772014B2

公开(公告)日：2010-08-10

申请号：US11845834

申请日：2007-08-28

Applicant: Kezhakkedath R. Udayakumar ,  Ted S. Moise ,  Qi-Du Jiang

Inventor： Kezhakkedath R. Udayakumar ,  Ted S. Moise ,  Qi-Du Jiang

IPC: H01L29/92

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/57

Abstract: One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein.

Abstract translation: 本发明的一个方面提供一种制造具有减少单位故障的FeRAM半导体器件的方法。 该方面包括在位于半导体衬底之上的电介质层内形成电接触，并在电介质层和电接触之上形成第一阻挡层。 第一阻挡层通过沉积多个阻挡层并在其沉积之后致密化每个阻挡层而形成。 这形成了具有相同元素组成的多个阻挡层的堆叠。 该方法还包括在第一阻挡层上形成第二阻挡层，并形成下电容器电极，在下电容器上形成铁电电介质层，以及在铁电介质层上形成上电容器电极。 本文还提供了通过该方法制造的装置。

公开(公告)号：US08779485B2

公开(公告)日：2014-07-15

申请号：US13480044

申请日：2012-05-24

Applicant: Kezhakkedath R. Udayakumar ,  Scott R. Summerfelt ,  Ted S. Moise ,  Manoj K. Jain

Inventor： Kezhakkedath R. Udayakumar ,  Scott R. Summerfelt ,  Ted S. Moise ,  Manoj K. Jain

IPC: H01L21/02 ,  H01L23/48 ,  H01L21/768 ,  H01L49/02 ,  H01L27/115

CPC classification number: H01L21/76843 ,  H01L27/11509 ,  H01L28/57

Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.

公开(公告)号：US20120241907A1

公开(公告)日：2012-09-27

申请号：US13485068

申请日：2012-05-31

Applicant: RAJNI J. AGGARWAL ,  SCOTT R. SUMMERFELT ,  GUL B. BASIM ,  TED S. MOISE

Inventor： RAJNI J. AGGARWAL ,  SCOTT R. SUMMERFELT ,  GUL B. BASIM ,  TED S. MOISE

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/57 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

Abstract: An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer.

Abstract translation: 包含铁电电容器，下伏氢屏障和上覆氢阻挡层的集成电路。 一种用于形成包含铁电电容器，下伏氢屏障和上覆氢阻挡层的集成电路的方法。

公开(公告)号：US20110079884A1

公开(公告)日：2011-04-07

申请号：US12890137

申请日：2010-09-24

Applicant: Gul B. Basim ,  Scott R. Summerfelt ,  Ted S. Moise

Inventor： Gul B. Basim ,  Scott R. Summerfelt ,  Ted S. Moise

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/31

CPC classification number: H01L21/3003 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

Abstract translation: 具有钝化捕获层的集成电路。 具有位于钝化捕获层下面的氢或氘释放层的集成电路。 用于形成具有氢或氘释放层的集成电路的方法。 用于形成具有钝化捕获层的集成电路的方法。

公开(公告)号：US20090057736A1

公开(公告)日：2009-03-05

申请号：US11845834

申请日：2007-08-28

Applicant: Kezhakkedath R. Udayakumar ,  Ted S. Moise ,  Qi-Du Jiang

Inventor： Kezhakkedath R. Udayakumar ,  Ted S. Moise ,  Qi-Du Jiang

IPC: H01L27/105 ,  H01L21/8239

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/57

Abstract: One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein.

Abstract translation: 本发明的一个方面提供一种制造具有减少单位故障的FeRAM半导体器件的方法。 该方面包括在位于半导体衬底之上的电介质层内形成电接触，并在电介质层和电接触之上形成第一阻挡层。 第一阻挡层通过沉积多个阻挡层并在其沉积之后致密化每个阻挡层而形成。 这形成了具有相同元素组成的多个阻挡层的堆叠。 该方法还包括在第一阻挡层上形成第二阻挡层，并形成下电容器电极，在下电容器上形成铁电电介质层，以及在铁电介质层上形成上电容器电极。 本文还提供了通过该方法制造的装置。

公开(公告)号：US08496842B2

公开(公告)日：2013-07-30

申请号：US13230350

申请日：2011-09-12

Applicant: Kezhakkedath R. Udayakumar ,  Marie Denison ,  Ted S. Moise

Inventor： Kezhakkedath R. Udayakumar ,  Marie Denison ,  Ted S. Moise

IPC: B44C1/22

CPC classification number: H01L41/08 ,  H01L27/20 ,  H01L41/0533 ,  H01L41/1134 ,  H01L41/1136 ,  H01L41/1138 ,  H01L41/22 ,  H01L41/318 ,  H01L2224/18

Abstract: A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element.

Abstract translation: 平面集成MEMS器件在连接到校准块的柔性元件上的介电隔离层上具有压电元件。 压电元件包含在隔离电介质上形成的具有钙钛矿结构的铁电元件。 在铁电元件上形成至少两个电极。 在压电元件上形成上部氢屏障。 在延伸到半导体衬底中的MEMS器件的周边形成有正面侧划分沟槽。 DRIE工艺从衬底的底侧去除材料以形成柔性元件，在正面单面沟槽之下从衬底去除材料，并从衬底材料形成校验物质。 压电元件与柔性元件重叠。

公开(公告)号：US08329588B2

公开(公告)日：2012-12-11

申请号：US13303541

申请日：2011-11-23

Applicant: Scott R. Summerfelt ,  Ted S. Moise ,  Gul B. Basim

Inventor： Scott R. Summerfelt ,  Ted S. Moise ,  Gul B. Basim

IPC: H01L21/311

CPC classification number: H01L21/3185 ,  H01L21/0217 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5223 ,  H01L27/11509 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region.

Abstract translation: 一种用于形成覆盖铁电电容器和缓冲区域但是从逻辑区域的一部分去除的氢阻挡层的方法。