公开(公告)号：US08329588B2

公开(公告)日：2012-12-11

申请号：US13303541

申请日：2011-11-23

Applicant: Scott R. Summerfelt ,  Ted S. Moise ,  Gul B. Basim

Inventor： Scott R. Summerfelt ,  Ted S. Moise ,  Gul B. Basim

IPC: H01L21/311

CPC classification number: H01L21/3185 ,  H01L21/0217 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5223 ,  H01L27/11509 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region.

Abstract translation: 一种用于形成覆盖铁电电容器和缓冲区域但是从逻辑区域的一部分去除的氢阻挡层的方法。

公开(公告)号：US20120175689A1

公开(公告)日：2012-07-12

申请号：US13396386

申请日：2012-02-14

Applicant: Gul B. Basim ,  Scott R. Summerfelt ,  Ted S. Moise

Inventor： Gul B. Basim ,  Scott R. Summerfelt ,  Ted S. Moise

IPC: H01L29/772

CPC classification number: H01L21/3003 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

公开(公告)号：US20120149189A1

公开(公告)日：2012-06-14

申请号：US13396420

申请日：2012-02-14

Applicant: Gul B. Basim ,  Scott R. Summerfelt ,  Ted S. Moise

Inventor： Gul B. Basim ,  Scott R. Summerfelt ,  Ted S. Moise

IPC: H01L21/768 ,  H01L21/31

CPC classification number: H01L21/3003 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

Abstract translation: 具有钝化捕获层的集成电路。 具有位于钝化捕获层下面的氢或氘释放层的集成电路。 用于形成具有氢或氘释放层的集成电路的方法。 用于形成具有钝化捕获层的集成电路的方法。

公开(公告)号：US20120241907A1

公开(公告)日：2012-09-27

申请号：US13485068

申请日：2012-05-31

Applicant: RAJNI J. AGGARWAL ,  SCOTT R. SUMMERFELT ,  GUL B. BASIM ,  TED S. MOISE

Inventor： RAJNI J. AGGARWAL ,  SCOTT R. SUMMERFELT ,  GUL B. BASIM ,  TED S. MOISE

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/57 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

Abstract: An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer.

Abstract translation: 包含铁电电容器，下伏氢屏障和上覆氢阻挡层的集成电路。 一种用于形成包含铁电电容器，下伏氢屏障和上覆氢阻挡层的集成电路的方法。

公开(公告)号：US20110079884A1

公开(公告)日：2011-04-07

申请号：US12890137

申请日：2010-09-24

Applicant: Gul B. Basim ,  Scott R. Summerfelt ,  Ted S. Moise

Inventor： Gul B. Basim ,  Scott R. Summerfelt ,  Ted S. Moise

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/31

CPC classification number: H01L21/3003 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

Abstract translation: 具有钝化捕获层的集成电路。 具有位于钝化捕获层下面的氢或氘释放层的集成电路。 用于形成具有氢或氘释放层的集成电路的方法。 用于形成具有钝化捕获层的集成电路的方法。

公开(公告)号：US08669644B2

公开(公告)日：2014-03-11

申请号：US12890137

申请日：2010-09-24

Applicant: Gul B. Basim ,  Scott R. Summerfelt ,  Ted S. Moise

Inventor： Gul B. Basim ,  Scott R. Summerfelt ,  Ted S. Moise

IPC: H01L23/522

CPC classification number: H01L21/3003 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/76829 ,  H01L21/76832 ,  H01L29/6659 ,  H01L29/7833

Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.

Abstract translation: 具有钝化捕获层的集成电路。 具有位于钝化捕获层下面的氢或氘释放层的集成电路。 用于形成具有氢或氘释放层的集成电路的方法。 用于形成具有钝化捕获层的集成电路的方法。

公开(公告)号：US08384190B2

公开(公告)日：2013-02-26

申请号：US12717604

申请日：2010-03-04

Applicant: Scott R. Summerfelt ,  Ted S. Moise ,  Gul B. Basim

Inventor： Scott R. Summerfelt ,  Ted S. Moise ,  Gul B. Basim

IPC: H01L21/02

CPC classification number: H01L21/3185 ,  H01L21/0217 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5223 ,  H01L27/11509 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit that includes a logic region, a buffer region, and a ferroelectric capacitor region that contains ferroelectric capacitors. The integrated circuit also includes a hydrogen diffusion barrier film that overlies ferroelectric capacitors and also overlies a buffer region located between a ferroelectric capacitor region and a logic region. However, the hydrogen diffusion barrier film is removed from a portion of the logic region. Moreover, a method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region.

Abstract translation: 一种包括逻辑区域，缓冲区域和包含铁电电容器的铁电电容器区域的集成电路。 集成电路还包括覆盖铁电电容器的氢扩散阻挡膜，并且还覆盖位于铁电电容器区域和逻辑区域之间的缓冲区域。 然而，氢扩散阻挡膜从逻辑区域的一部分去除。 此外，形成氢屏障层的方法，该阻挡层覆盖铁电电容器和缓冲区域，但是从逻辑区域的一部分去除。

公开(公告)号：US20100224961A1

公开(公告)日：2010-09-09

申请号：US12717604

申请日：2010-03-04

Applicant: Scott R. Summerfelt ,  Ted S. Moise ,  Gul B. Basim

Inventor： Scott R. Summerfelt ,  Ted S. Moise ,  Gul B. Basim

IPC: H01L29/92 ,  H01L21/302

CPC classification number: H01L21/3185 ,  H01L21/0217 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5223 ,  H01L27/11509 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit that includes a logic region, a buffer region, and a ferroelectric capacitor region that contains ferroelectric capacitors. The integrated circuit also includes a hydrogen diffusion barrier film that overlies ferroelectric capacitors and also overlies a buffer region located between a ferroelectric capacitor region and a logic region. However, the hydrogen diffusion barrier film is removed from a portion of the logic region. Moreover, a method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region.

Abstract translation: 一种包括逻辑区域，缓冲区域和包含铁电电容器的铁电电容器区域的集成电路。 集成电路还包括覆盖铁电电容器的氢扩散阻挡膜，并且还覆盖位于铁电电容器区域和逻辑区域之间的缓冲区域。 然而，氢扩散阻挡膜从逻辑区域的一部分去除。 此外，形成氢屏障层的方法，该阻挡层覆盖铁电电容器和缓冲区域，但是从逻辑区域的一部分去除。

公开(公告)号：US20120070993A1

公开(公告)日：2012-03-22

申请号：US13303541

申请日：2011-11-23

Applicant: Scott R. Summerfelt ,  Ted S. Moise ,  Gul B. Basim

Inventor： Scott R. Summerfelt ,  Ted S. Moise ,  Gul B. Basim

IPC: H01L21/31

CPC classification number: H01L21/3185 ,  H01L21/0217 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5223 ,  H01L27/11509 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region.

Abstract translation: 一种用于形成覆盖铁电电容器和缓冲区域但是从逻辑区域的一部分去除的氢阻挡层的方法。

公开(公告)号：US20110079878A1

公开(公告)日：2011-04-07

申请号：US12890219

申请日：2010-09-24

Applicant: Rajni J. Aggarwal ,  Scott R. Summerfelt ,  Gul B. Basim ,  Ted S. Moise

Inventor： Rajni J. Aggarwal ,  Scott R. Summerfelt ,  Gul B. Basim ,  Ted S. Moise

IPC: H01L29/92 ,  H01L21/00

CPC classification number: H01L28/57 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

Abstract: An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer.

Abstract translation: 包含铁电电容器，下伏氢屏障和上覆氢阻挡层的集成电路。 一种用于形成包含铁电电容器，下伏氢屏障和上覆氢阻挡层的集成电路的方法。