公开(公告)号：US5103275A

公开(公告)日：1992-04-07

申请号：US617613

申请日：1990-11-26

申请人： Atsushi Miura ,  Tatsushi Yusuki

发明人： Atsushi Miura ,  Tatsushi Yusuki

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10817

摘要： A semiconductor memory comprising a plurality of memory cells including transistors provided on a semiconductor substrate and capacitors having upper electrodes, insulating films and lower electrodes provided on the transistors, one terminal of the transistor of the memory cell being connected to the lower electrode of the capacitor, wherein the capacitors of the adjacent memory cells are opposed to each other, a part of the capacitors being superposed perpendicularly to the semiconductor substrate.

摘要翻译： 一种半导体存储器，包括多个存储单元，包括设置在半导体衬底上的晶体管和设置在晶体管上的上电极，绝缘膜和下电极的电容器，存储单元的晶体管的一个端子连接到电容器的下电极 其中相邻存储单元的电容器彼此相对，一部分电容器垂直于半导体衬底重叠。

公开(公告)号：US5357460A

公开(公告)日：1994-10-18

申请号：US888856

申请日：1992-05-27

申请人： Tatsushi Yusuki ,  Shigeo Onishi ,  Kenichi Tanaka ,  Keizo Sakiyama ,  Katsuji Iguchi

发明人： Tatsushi Yusuki ,  Shigeo Onishi ,  Kenichi Tanaka ,  Keizo Sakiyama ,  Katsuji Iguchi

IPC分类号： G11C11/22 ,  H01L27/115

CPC分类号： H01L27/11502 ,  G11C11/22

摘要： A semiconductor memory device which comprises unit memory cells each including two transistors each having a source/drain region and a gate electrode and one capacitor having a capacitor dielectric film, an upper electrode and a lower electrode, the gate electrode of each transistor being connected to a common word line, one source/drain region of each transistor being connected to a bit line and a reversed bit line respectively and the other source/drain region being connected to the upper electrode and the lower electrode respectively, and the bit line, the reversed bit line and the word line being disposed under the lower electrode of the capacitor.

摘要翻译： 一种半导体存储器件，包括单元存储单元，每个单元存储单元包括每个具有源/漏区和栅电极的两个晶体管，以及一个具有电容器电介质膜的电容器，上电极和下电极，每个晶体管的栅电极连接到 公共字线，每个晶体管的一个源极/漏极区分别连接到位线和反向位线，另一个源极/漏极区分别连接到上部电极和下部电极，位线， 反转的位线和字线被布置在电容器的下电极之下。

公开(公告)号：US5309386A

公开(公告)日：1994-05-03

申请号：US699348

申请日：1991-05-13

申请人： Tatsushi Yusuki ,  Atsushi Miura ,  Kenichi Tanaka

发明人： Tatsushi Yusuki ,  Atsushi Miura ,  Kenichi Tanaka

IPC分类号： H01L27/108 ,  G11C5/02 ,  G11C11/24

CPC分类号： H01L27/10808

摘要： A semiconductor memory wherein a plurality of cells are arranged in a longitudinal direction of active regions, each cell having a node electrode and a contact hole for the node electrode, and a bit line contact region and the active region by half at the least on a semiconductor substrate having the active regions and word lines which are extended in a direction perpendicular to the longitudinal direction of the active regions, the bit line contact regions of adjacent bit lines are shifted by a quarter in the longitudinal direction between the adjacent cells in a direction in which the word lines are extended, and the projected shape of the node electrode is a polygon having more angles than a quadrangle which is substantially adapted as the node electrode and having at least one of interior angles set to be obtuse so that the projected area is substantially larger than that of the quadrangle.

摘要翻译： 一种半导体存储器，其中多个单元沿有源区的纵向布置，每个单元具有节点电极和用于节点电极的接触孔，并且位线接触区域和有源区域至少在一个 半导体衬底具有在与有源区的纵向方向垂直的方向上延伸的有源区和字线，相邻位线的位线接触区在相邻单元之间沿纵向方向在方向上偏移四分之一 其中字线延伸，并且节点电极的投影形状是具有比基本适合作为节点电极的四边形更多的角度的多边形，并且具有被设置为钝的至少一个内角，使得投影面积 大大地大于四边形。