公开(公告)号：US5886377A

公开(公告)日：1999-03-23

申请号：US812539

申请日：1997-03-07

申请人： Masataka Tsuruta ,  Noriyuki Shimoji ,  Takuya Yonezawa

发明人： Masataka Tsuruta ,  Noriyuki Shimoji ,  Takuya Yonezawa

IPC分类号： H01L21/82 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825

摘要： An ONO layer 18 located vicinity of a transistor TR1 for programming is removed. A floating gate FG1 of the transistor TR1 is formed by carrying out etching of a polysilicon layer 16. Then, an inter-layer film SM1 of the transistor TR1 is formed by carrying out oxidation process. The inter-layer film SM1 is formed so as to cover the floating gate FG1. Arsenic is implanted ionically into a semiconductor-substrate 12 using the floating gate FG1 and the inter-layer film SM1 as a mask. Ions of the arsenic thus implanted do not pass through the inter-layer film SM1 and are stopped at the surface. Because the inter-layer film SM1 is made of a silicon oxidation layer formed relatively thick. So that, the inter-layer film SM1 maintains its charge-storage characteristic originally owns even when the ion implantation is carried out.

公开(公告)号：US6130130A

公开(公告)日：2000-10-10

申请号：US208534

申请日：1998-12-09

申请人： Masataka Tsuruta ,  Noriyuki Shimoji ,  Takuya Yonezawa

发明人： Masataka Tsuruta ,  Noriyuki Shimoji ,  Takuya Yonezawa

IPC分类号： H01L21/82 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825

摘要： An ONO layer 18 located vicinity of a transistor TR1 for programming is removed. A floating gate FG1 of the transistor TR1 is formed by carrying out etching of a polysilicon layer 16. Then, an inter-layer film SM1 of the transistor TR1 is formed by carrying out oxidation process. The inter-layer film SM1 is formed so as to cover the floating gate FG1. Arsenic is implanted ionically into a semiconductor-substrate 12 using the floating gate FG1 and the inter-layer film SM1 as a mask. Ions of the arsenic thus implanted do not pass through the inter-layer film SM1 and are stopped at the surface. Because the inter-layer film SM1 is made of a silicon oxidation layer formed relatively thick. So that, the inter-layer film SM1 maintains its charge-storage characteristic originally owns even when the ion implantation is carried out.

摘要翻译： 位于用于编程的晶体管TR1的附近的ONO层18被去除。 通过进行多晶硅层16的蚀刻来形成晶体管TR1的浮置栅极FG1。然后，通过进行氧化处理形成晶体管TR1的层间膜SM1。 层间膜SM1形成为覆盖浮栅FG1。 使用浮栅FG1和层间膜SM1作为掩模将砷离子注入到半导体衬底12中。 这样植入的砷离子不会通过层间膜SM1而停止在表面。 因为层间膜SM1由相对较厚的硅氧化层制成。 因此，即使进行离子注入，层间膜SM1也保持原来的电荷存储特性。

公开(公告)号：US5985716A

公开(公告)日：1999-11-16

申请号：US718275

申请日：1996-09-20

申请人： Noriyuki Shimoji ,  Masataka Tsuruta ,  Takuya Yonezawa

发明人： Noriyuki Shimoji ,  Masataka Tsuruta ,  Takuya Yonezawa

IPC分类号： H01L21/82 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  Y10S438/97

摘要： A polysilicon layer 38 located upward of a local oxidation of silicon (LOCOS) layer 20 is removed partially when selective etching of the polysilicon layer 38 for forming a floating gate FG is carried out by carrying out anisotropic etching. The etching is stopped when only the polysilicon layer 38 is removed. Wet-etching usually carried out at the final phase of the anisotropic etching process is not performed. In this way, the LOCOS layer 20 located underneath the polysilicon layer 38 is not over-etched. As a result, an inter layer 34 is not formed in a shape of eaves on the LOCOS layer 20 when the inter layer 34 is formed. Therefore, the probability of causing stringers underneath the inter layer 34 is remarkably low.

摘要翻译： 当通过进行各向异性蚀刻来执行用于形成浮栅FG的多晶硅层38的选择性蚀刻时，部分地去除位于硅（LOCOS）层20的局部氧化之上的多晶硅层38。 当仅去除多晶硅层38时停止蚀刻。 通常在各向异性蚀刻处理的最后阶段进行的湿法蚀刻不进行。 以这种方式，位于多晶硅层38下面的LOCOS层20不会被过度蚀刻。 结果，当形成层间34时，层间34不形成在LOCOS层20上的屋檐形状。 因此，在层间34之下引起桁条的概率非常低。