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公开(公告)号：US20050230796A1
公开(公告)日：2005-10-20
申请号：US11105482
申请日：2005-04-14
Applicant: Noriaki Sakamoto , Takehisa Yokohama , Tomoru Sato , Takafumi Kikuchi , Fujio Ito
Inventor： Noriaki Sakamoto , Takehisa Yokohama , Tomoru Sato , Takafumi Kikuchi , Fujio Ito
IPC: G01R31/28 , G11C29/00 , G11C29/56 , H01L21/822 , H01L23/02 , H01L23/31 , H01L23/495 , H01L23/544 , H01L25/18 , H01L27/04
CPC classification number: H01L24/49 , H01L22/34 , H01L23/3128 , H01L23/49575 , H01L24/32 , H01L24/45 , H01L24/48 , H01L25/18 , H01L2224/05554 , H01L2224/29007 , H01L2224/32014 , H01L2224/32245 , H01L2224/45099 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/4943 , H01L2224/73265 , H01L2224/92247 , H01L2225/06596 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01055 , H01L2924/01079 , H01L2924/01082 , H01L2924/10161 , H01L2924/10162 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2924/3512 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
Abstract: To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP 102 constituted by mounting a plurality of semiconductor chips to a signal package of ASIC 100, SDRAM 101 and the like, a circuit of testing SDRAM 101 (SDRAMBIST 109) is provided at inside of ASIC 100, and SDRAM 101 is tested from outside of SDRAM 101, that is, from ASIC 100. By providing the test circuit of SDRAM 101 at inside of ASIC 100, it is not necessary to extrude a terminal for testing SDRAM 101 to outside of SIP 102.
Abstract translation: 为了提供一种测试技术，能够通过将通过将多个半导体芯片安装到单个封装构成的SIP等的半导体集成电路中的多个端子（引脚）减少到封装尺寸，在通过安装 将多个半导体芯片连接到ASIC 100，SDRAM 101等的信号封装，在ASIC 100的内部提供测试SDRAM 101（SDRAMBIST 109）的电路，并且从RAM 101的外部测试SDRAM 101， 通过在ASIC100的内部提供SDRAM 101的测试电路，不需要将用于测试SDRAM 101的终端拉伸到SIP 102的外部。
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公开(公告)号：US20070120237A1
公开(公告)日：2007-05-31
申请号：US11698104
申请日：2007-01-26
Applicant: Noriaki Sakamoto , Takehisa Yokohama , Tomoru Sato , Takafumi Kikuchi , Fujio Ito
Inventor： Noriaki Sakamoto , Takehisa Yokohama , Tomoru Sato , Takafumi Kikuchi , Fujio Ito
IPC: H01L23/495
CPC classification number: H01L24/49 , H01L22/34 , H01L23/3128 , H01L23/49575 , H01L24/32 , H01L24/45 , H01L24/48 , H01L25/18 , H01L2224/05554 , H01L2224/29007 , H01L2224/32014 , H01L2224/32245 , H01L2224/45099 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/4943 , H01L2224/73265 , H01L2224/92247 , H01L2225/06596 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01055 , H01L2924/01079 , H01L2924/01082 , H01L2924/10161 , H01L2924/10162 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2924/3512 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
Abstract: To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP 102 constituted by mounting a plurality of semiconductor chips to a signal package of ASIC 100, SDRAM 101 and the like, a circuit of testing SDRAM 101 (SDRAMBIST 109) is provided at inside of ASIC 100, and SDRAM 101 is tested from outside of SDRAM 101, that is, from ASIC 100. By providing the test circuit of SDRAM 101 at inside of ASIC 100, it is not necessary to extrude a terminal for testing SDRAM 101 to outside of SIP 102.
Abstract translation: 为了提供一种测试技术，能够通过将通过将多个半导体芯片安装到单个封装构成的SIP等的半导体集成电路中的多个端子（引脚）减少到封装尺寸，在通过安装 将多个半导体芯片连接到ASIC 100，SDRAM 101等的信号封装，在ASIC 100的内部提供测试SDRAM 101（SDRAMBIST 109）的电路，并且从RAM 101的外部测试SDRAM 101， 来自ASIC 100。 通过在ASIC100的内部提供SDRAM 101的测试电路，不需要将用于测试SDRAM 101的终端拉伸到SIP 102的外部。
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公开(公告)号：US5896025A
公开(公告)日：1999-04-20
申请号：US777965
申请日：1996-12-24
Applicant: Takeshi Yamaguchi , Yosifumi Sakaguchi , Shinji Tanaka , Takehisa Yokohama , Kouichi Horisaki , Eiji Matsumasa
Inventor： Takeshi Yamaguchi , Yosifumi Sakaguchi , Shinji Tanaka , Takehisa Yokohama , Kouichi Horisaki , Eiji Matsumasa
CPC classification number: H02J7/0031
Abstract: A protection circuit device for protecting a secondary battery from an overcharge and/or an overdischarge has first and second terminals, across which a charger and a load are alternatively connectable. A first switch and/or a second switch may be provided in series with the secondary battery between the first and second terminals. In a charging operation mode, the second switch is kept conductive. A charging operation is performed with the first switch made conductive. When the battery is overcharged for some reasons, the first switch is turned off. Upon connection of a load across the first and second terminals, the first switch is restored to a conductive state for a discharging operation which releases the battery from an overdischarge state. In a discharging operation mode, the first switch is kept conductive. A discharge operation is performed with the second switch made conductive. When the battery is overdischarged, the second switch is caused to remain conductive even after commencement of the overdischarge, so that the battery can continue the discharge operation if the temporary overdischarge does not last longer than the predetermined period of time.
Abstract translation: 用于保护二次电池免受过充电和/或过放电的保护电路装置具有第一和第二端子，充电器和负载可交替地连接在该端子上。 可以在第一和第二端子之间与二次电池串联地提供第一开关和/或第二开关。 在充电操作模式中，第二开关保持导通。 在第一开关导通的情况下执行充电操作。 当电池由于某些原因过充电时，第一个开关关闭。 当跨越第一和第二端子的负载连接时，第一开关被恢复到用于使电池从过放电状态释放的放电操作的导通状态。 在放电操作模式中，第一开关保持导通。 在第二开关导通时执行放电操作。 当电池过度放电时，即使在过放电开始之后，第二开关也保持导通，使得如果临时过放电持续时间比预定时间长，电池可以继续放电操作。
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公开(公告)号：US07176487B2
公开(公告)日：2007-02-13
申请号：US11105482
申请日：2005-04-14
Applicant: Noriaki Sakamoto , Takehisa Yokohama , Tomoru Sato , Takafumi Kikuchi , Fujio Ito
Inventor： Noriaki Sakamoto , Takehisa Yokohama , Tomoru Sato , Takafumi Kikuchi , Fujio Ito
CPC classification number: H01L24/49 , H01L22/34 , H01L23/3128 , H01L23/49575 , H01L24/32 , H01L24/45 , H01L24/48 , H01L25/18 , H01L2224/05554 , H01L2224/29007 , H01L2224/32014 , H01L2224/32245 , H01L2224/45099 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/4943 , H01L2224/73265 , H01L2224/92247 , H01L2225/06596 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01047 , H01L2924/01055 , H01L2924/01079 , H01L2924/01082 , H01L2924/10161 , H01L2924/10162 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2924/3512 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
Abstract: To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP 102 constituted by mounting a plurality of semiconductor chips to a signal package of ASIC 100, SDRAM 101 and the like, a circuit of testing SDRAM 101 (SDRAMBIST 109) is provided at inside of ASIC 100, and SDRAM 101 is tested from outside of SDRAM 101, that is, from ASIC 100. By providing the test circuit of SDRAM 101 at inside of ASIC 100, it is not necessary to extrude a terminal for testing SDRAM 101 to outside of SIP 102.
Abstract translation: 为了提供一种测试技术，能够通过将通过将多个半导体芯片安装到单个封装构成的SIP等的半导体集成电路中的多个端子（引脚）减少到封装尺寸，在通过安装 将多个半导体芯片连接到ASIC 100，SDRAM 101等的信号封装，在ASIC 100的内部提供测试SDRAM 101（SDRAMBIST 109）的电路，并且从RAM 101的外部测试SDRAM 101， 通过在ASIC100的内部提供SDRAM 101的测试电路，不需要将用于测试SDRAM 101的终端拉伸到SIP 102的外部。
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