公开(公告)号：US20050195864A1

公开(公告)日：2005-09-08

申请号：US11100335

申请日：2005-04-06

申请人： Hiroyuki Matsuo ,  Mitsuhiro Kawaguchi ,  Shosaku Yamasaki ,  Takashi Umegaki ,  Koji Komatsu ,  Yoshimasa Itsuki

发明人： Hiroyuki Matsuo ,  Mitsuhiro Kawaguchi ,  Shosaku Yamasaki ,  Takashi Umegaki ,  Koji Komatsu ,  Yoshimasa Itsuki

IPC分类号： H04J1/16 ,  H04L1/00 ,  H04L12/26 ,  H04L12/437

CPC分类号： H04L12/437

摘要： An apparatus has a cross connection circuit, first switching sections located on the input side of the cross connection circuit to switch a presently-used transmission path and a reserve transmission path, and second switching sections located on the output side of the cross connection circuit to switch the presently-used transmission path and the reserve transmission path and comprises slot sections, first selecting section selectively connecting any one of the slot sections to the input side of the first switching section, second selecting section connecting the output side of the first switching section to the input side of the cross connection circuit, third selecting section selectively connecting the output side of the cross connection circuit to the input side of any of the second switching sections, and fourth selecting section connecting the output side of the second switching section to any one of the slot sections.

摘要翻译： 一种装置具有交叉连接电路，位于交叉连接电路的输入侧的第一开关部分，用于切换当前使用的传输路径和预留传输路径，以及位于交叉连接电路的输出侧的第二开关部分， 切换当前使用的传输路径和预留传输路径，并且包括时隙部分，第一选择部分选择性地连接任一个时隙部分到第一切换部分的输入侧;第二选择部分，连接第一切换部分的输出侧 到交叉连接电路的输入侧，第三选择部选择性地将交叉连接电路的输出侧连接到任何第二切换部的输入侧，第四选择部将第二切换部的输出侧连接到 其中一个插槽部分。

公开(公告)号：US08564355B2

公开(公告)日：2013-10-22

申请号：US13004438

申请日：2011-01-11

申请人： Shigeo Tani ,  Takashi Umegaki

发明人： Shigeo Tani ,  Takashi Umegaki

IPC分类号： H03K3/00

CPC分类号： G06F1/06 ,  G06F11/0754 ,  H03L7/095 ,  H03L7/22

摘要： There is provided a clock device including: a clock circuit to generate a plurality of clock signals, the clock circuit including a reset part for resetting generation of the clock signals; and a peripheral circuit operating based on the clock signals generated from the clock circuit, the peripheral circuit including: an error detection part for detecting an error in a process performed in the peripheral circuit by using the clock signals, and a determination part for determining whether to reset the clock circuit, based on information of the error detected by the error detection part.

摘要翻译： 提供了一种时钟装置，包括：产生多个时钟信号的时钟电路，所述时钟电路包括用于复位时钟信号的产生的复位部分; 以及基于从时钟电路产生的时钟信号而工作的外围电路，所述外围电路包括：误差检测部，其通过使用所述时钟信号来检测在所述外围电路中执行的处理中的错误;判定部， 基于由错误检测部检测到的错误的信息来复位时钟电路。

公开(公告)号：US08295161B2

公开(公告)日：2012-10-23

申请号：US12639086

申请日：2009-12-16

申请人： Ryoji Azumi ,  Takashi Umegaki ,  Shigeo Tani ,  Shosaku Yamasaki

发明人： Ryoji Azumi ,  Takashi Umegaki ,  Shigeo Tani ,  Shosaku Yamasaki

IPC分类号： H04L1/22

CPC分类号： H04J3/14 ,  H04J2203/006

摘要： A network apparatus includes: an input interface unit; a first and second line switching units cross-connecting output signals from the input interface unit; an output interface unit including a selection unit selecting outputs from the first or second line switching units; and a CPU. The line switching units each include: a control signal generation unit storing setting data in a memory and generating a line switching control signal based on the setting data; a memory error detection processing unit detecting a memory error and outputting error information; and a main signal processing unit writing setting data into a buffer when an error is not detected, and holding setting data stored in the buffer when the error is detected, and which performs cross-connection processing according to the setting data stored in the buffer. The CPU controls the selection unit according to the error information.

摘要翻译： 网络装置包括：输入接口单元; 第一和第二线路交换单元将来自输入接口单元的输出信号交叉连接; 输出接口单元，包括：选择单元，用于选择来自第一或第二行切换单元的输出; 和一个CPU。 线路切换单元各自包括：控制信号生成单元，其将设置数据存储在存储器中，并且基于设置数据生成线路切换控制信号; 存储器错误检测处理单元，检测存储器错误并输出错误信息; 以及主信号处理单元，当未检测到错误时将设置数据写入缓冲器，并且当检测到错误时保持存储在缓冲器中的设置数据，并且根据存储在缓冲器中的设置数据执行交叉连接处理。 CPU根据错误信息控制选择单元。

公开(公告)号：US20100158514A1

公开(公告)日：2010-06-24

申请号：US12639086

申请日：2009-12-16

申请人： Ryoji AZUMI ,  Takashi Umegaki ,  Shigeo Tani ,  Shosaku Yamasaki

发明人： Ryoji AZUMI ,  Takashi Umegaki ,  Shigeo Tani ,  Shosaku Yamasaki

IPC分类号： H04B10/08 ,  H04B10/02

CPC分类号： H04J3/14 ,  H04J2203/006

摘要： A network apparatus includes: an input interface unit; a first and second line switching units cross-connecting output signals from the input interface unit; an output interface unit including a selection unit selecting outputs from the first or second line switching units; and a CPU. The line switching units each include: a control signal generation unit storing setting data in a memory and generating a line switching control signal based on the setting data; a memory error detection processing unit detecting a memory error and outputting error information; and a main signal processing unit writing setting data into a buffer when an error is not detected, and holding setting data stored in the buffer when the error is detected, and which performs cross-connection processing according to the setting data stored in the buffer. The CPU controls the selection unit according to the error information.

摘要翻译： 网络装置包括：输入接口单元; 第一和第二线路交换单元将来自输入接口单元的输出信号交叉连接; 输出接口单元，包括：选择单元，用于选择来自第一或第二行切换单元的输出; 和一个CPU。 线路切换单元各自包括：控制信号生成单元，其将设置数据存储在存储器中，并且基于设置数据生成线路切换控制信号; 存储器错误检测处理单元，检测存储器错误并输出错误信息; 以及主信号处理单元，当未检测到错误时将设置数据写入缓冲器，并且当检测到错误时保持存储在缓冲器中的设置数据，并且根据存储在缓冲器中的设置数据执行交叉连接处理。 CPU根据错误信息控制选择单元。

公开(公告)号：US5557437A

公开(公告)日：1996-09-17

申请号：US487444

申请日：1995-06-07

申请人： Toshiharu Sakai ,  Yoshinori Nakamura ,  Takashi Umegaki ,  Nobuo Iguchi ,  Miki Hagino ,  Hiroaki Mori ,  Toshikazu Ota ,  Akihiko Oka ,  Kazuo Takatsu ,  Nobuyuki Nemoto

发明人： Toshiharu Sakai ,  Yoshinori Nakamura ,  Takashi Umegaki ,  Nobuo Iguchi ,  Miki Hagino ,  Hiroaki Mori ,  Toshikazu Ota ,  Akihiko Oka ,  Kazuo Takatsu ,  Nobuyuki Nemoto

IPC分类号： H04B10/035 ,  H04B10/07 ,  H04B10/077 ,  H04B10/08 ,  H04B10/00

CPC分类号： H04B10/075 ,  H04B10/079

摘要： An optical terminal system having self-monitoring function is disclosed, which includes a high-level group loopback section for internally looping back a serial electric signal, a low-level group loopback section for internally looping back a parallel electric signal, a self-loop section for connecting a receiver device and a transmitter device to loop an electric signal received by the receiver device directly to the transmitter device, and a self-monitoring controller for performing a self-monitoring test on respective components of the receiver device and transmitter device by using the self-loop section and either one of the high-level group loopback section and the low-level group loopback section. The optical terminal system can selfcheck the functions thereof through self-monitoring without depending on a network.

摘要翻译： 公开了一种具有自我监测功能的光学终端系统，其包括用于内部循环串行电信号的高级组环回部分，用于内部环回并行电信号的低级组环回部分，自回路 用于连接接收机设备和发射机设备的部分，以将由接收机设备接收的电信号直接发送到发射机设备;以及自监控控制器，用于通过接收机设备和发射机设备的各个组件执行自我监测测试， 使用自环路部分和高级组环回部分和低级组环回部分之一。 光学终端系统可以通过自我监视来自行检查其功能，而不依赖于网络。

公开(公告)号：US20110175653A1

公开(公告)日：2011-07-21

申请号：US13004438

申请日：2011-01-11

申请人： SHIGEO TANI ,  TAKASHI UMEGAKI

发明人： SHIGEO TANI ,  TAKASHI UMEGAKI

IPC分类号： H03L7/06 ,  G06F1/04

CPC分类号： G06F1/06 ,  G06F11/0754 ,  H03L7/095 ,  H03L7/22

摘要： There is provided a clock device including: a clock circuit to generate a plurality of clock signals, the clock circuit including a reset part for resetting generation of the clock signals; and a peripheral circuit operating based on the clock signals generated from the clock circuit, the peripheral circuit including: an error detection part for detecting an error in a process performed in the peripheral circuit by using the clock signals, and a determination part for determining whether to reset the clock circuit, based on information of the error detected by the error detection part.

摘要翻译： 提供了一种时钟装置，包括：产生多个时钟信号的时钟电路，所述时钟电路包括用于复位时钟信号的产生的复位部分; 以及基于从时钟电路产生的时钟信号而工作的外围电路，所述外围电路包括：误差检测部，其通过使用所述时钟信号来检测在所述外围电路中执行的处理中的错误;以及判定部， 基于由错误检测部检测到的错误的信息来复位时钟电路。

公开(公告)号：US07443843B2

公开(公告)日：2008-10-28

申请号：US11100335

申请日：2005-04-06

申请人： Hiroyuki Matsuo ,  Mitsuhiro Kawaguchi ,  Shosaku Yamasaki ,  Takashi Umegaki ,  Koji Komatsu ,  Yoshimasa Itsuki

发明人： Hiroyuki Matsuo ,  Mitsuhiro Kawaguchi ,  Shosaku Yamasaki ,  Takashi Umegaki ,  Koji Komatsu ,  Yoshimasa Itsuki

IPC分类号： H04Q11/00

CPC分类号： H04L12/437

摘要： An apparatus has a cross connection circuit, first switching sections located on the input side of the cross connection circuit to switch a presently-used transmission path and a reserve transmission path, and second switching sections located on the output side of the cross connection circuit to switch the presently-used transmission path and the reserve transmission path and comprises slot sections, first selecting section selectively connecting any one of the slot sections to the input side of the first switching section, second selecting section connecting the output side of the first switching section to the input side of the cross connection circuit, third selecting section selectively connecting the output side of the cross connection circuit to the input side of any of the second switching sections, and fourth selecting section connecting the output side of the second switching section to any one of the slot sections.

摘要翻译： 一种装置具有交叉连接电路，位于交叉连接电路的输入侧的第一开关部分，用于切换当前使用的传输路径和预留传输路径，以及位于交叉连接电路的输出侧的第二开关部分， 切换当前使用的传输路径和预留传输路径，并且包括时隙部分，第一选择部分选择性地连接任一个时隙部分到第一切换部分的输入侧;第二选择部分，连接第一切换部分的输出侧 到交叉连接电路的输入侧，第三选择部选择性地将交叉连接电路的输出侧连接到任何第二切换部的输入侧，第四选择部将第二切换部的输出侧连接到 其中一个插槽部分。

公开(公告)号：US09277299B2

公开(公告)日：2016-03-01

申请号：US13571461

申请日：2012-08-10

申请人： Shigeo Tani ,  Takashi Umegaki

发明人： Shigeo Tani ,  Takashi Umegaki

IPC分类号： G02B6/26 ,  G02B6/42 ,  G02B6/28 ,  H04Q11/00

CPC分类号： H04Q11/00 ,  H04Q2213/1301 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13367

摘要： A line switching device includes multiple input ports to which signals are input and that include first input ports and second input ports different from the first input ports; multiple output ports that include given output ports; a branch unit that branches first signals input from the first input ports; and a switch that selectively outputs, among second signals input from the second input ports and branched signals branched from the first signals by the branch unit, signals that are to be switched to an output port among the given ports.

摘要翻译： 线路切换装置包括输入信号的多个输入端口，并且包括与第一输入端口不同的第一输入端口和第二输入端口; 多个输出端口，包括给定的输出端口; 分支单元，分支从第一输入端口输入的第一信号; 以及开关，其在从所述第二输入端口输入的第二信号和由所述分支单元从所述第一信号分支的分支信号之间选择性地输出将被切换到所述给定端口中的输出端口的信号。

公开(公告)号：US20130094805A1

公开(公告)日：2013-04-18

申请号：US13571461

申请日：2012-08-10

申请人： Shigeo TANI ,  Takashi Umegaki

发明人： Shigeo TANI ,  Takashi Umegaki

IPC分类号： G02B6/35

CPC分类号： H04Q11/00 ,  H04Q2213/1301 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13367

摘要： A line switching device includes multiple input ports to which signals are input and that include first input ports and second input ports different from the first input ports; multiple output ports that include given output ports; a branch unit that branches first signals input from the first input ports; and a switch that selectively outputs, among second signals input from the second input ports and branched signals branched from the first signals by the branch unit, signals that are to be switched to an output port among the given ports.

摘要翻译： 线路切换装置包括输入信号的多个输入端口，并且包括与第一输入端口不同的第一输入端口和第二输入端口; 多个输出端口，包括给定的输出端口; 分支单元，分支从第一输入端口输入的第一信号; 以及开关，其在从所述第二输入端口输入的第二信号和由所述分支单元从所述第一信号分支的分支信号之间选择性地输出将被切换到所述给定端口中的输出端口的信号。

公开(公告)号：US20110170864A1

公开(公告)日：2011-07-14

申请号：US12987672

申请日：2011-01-10

申请人： Shigeo TANI ,  Hidenori Kiuchi ,  Takashi Umegaki ,  Ryoji Azumi ,  Shigehisa Sakahara

发明人： Shigeo TANI ,  Hidenori Kiuchi ,  Takashi Umegaki ,  Ryoji Azumi ,  Shigehisa Sakahara

IPC分类号： H04J14/00

CPC分类号： H04J3/1652

摘要： An interface device for demultiplexing, from a first frame in a transport network, a plurality of second frames multiplexed into the first frame is provided. The interface device includes an extractor configured to extract a plurality of data groups to constitute the first frame, and a second frame generator configured to create the second frames based on the plurality of data groups extracted by the extractor.

摘要翻译： 提供了一种用于从传输网络中的第一帧解复用多路复用到第一帧中的多个第二帧的接口设备。 接口装置包括提取器，被配置为提取多个数据组以构成第一帧;以及第二帧生成器，被配置为基于由提取器提取的多个数据组来创建第二帧。