公开(公告)号：US06453248B1

公开(公告)日：2002-09-17

申请号：US09119792

申请日：1998-07-21

申请人： David G. Hart ,  Damir Novosel ,  Steven A. Kunsman

发明人： David G. Hart ,  Damir Novosel ,  Steven A. Kunsman

IPC分类号： G01R3100

CPC分类号： G01R31/088 ,  G01R31/085 ,  G01R31/086 ,  H02H1/0015 ,  Y04S10/522

摘要： An improved high impedance fault (HIF) detection system comprises an analyzer located at a circuit breaker or substation with feeders, wherein the analyzer analyzes current and/or voltage waveforms to detect a HIF on the feeder or on one of a plurality of laterals coupled to the feeder; a plurality of remote outage detectors located respectively at corresponding customer sites, each remote outage detector including a mechanism to detect a loss of potential or power at the corresponding site; and a computer in communication with the analyzer and the remote outage detectors.

摘要翻译： 改进的高阻抗故障（HIF）检测系统包括位于具有馈线的断路器或变电站的分析仪，其中分析器分析电流和/或电压波形，以检测馈线上的HIF或多个耦合到 进料器; 分别位于相应的客户位置的多个远程停机检测器，每个远程停电检测器包括用于检测对应站点的电位或电力损失的机构; 以及与分析仪和远程停机检测器通信的计算机。

公开(公告)号：US07272515B2

公开(公告)日：2007-09-18

申请号：US11081042

申请日：2005-03-15

申请人： John M. Peterson ,  Steven A. Kunsman ,  Mohamed Y Haj-Maharsi ,  Reynaldo Nuqui ,  James Stoupis

发明人： John M. Peterson ,  Steven A. Kunsman ,  Mohamed Y Haj-Maharsi ,  Reynaldo Nuqui ,  James Stoupis

IPC分类号： G01R31/00

CPC分类号： H02H1/0015 ,  H02H1/0053 ,  H02H1/0092

摘要： A digital signal processor implementation of three algorithms used to detect high impedance faults. The algorithms can be wavelet based, higher order statistics based and neural network based. The algorithms are modified to process one second of data instead of ten seconds of data and a double buffered acquisition is connected to the output of the algorithms.

摘要翻译： 一种用于检测高阻抗故障的三种算法的数字信号处理器实现。 算法可以基于小波，基于高阶统计和神经网络。 这些算法被修改为处理数据的一秒而不是十秒的数据，并且双缓冲采集被连接到算法的输出。

公开(公告)号：US07069116B2

公开(公告)日：2006-06-27

申请号：US10770270

申请日：2004-02-02

申请人： Steven A. Kunsman ,  Ismail I. Jouny ,  Stephen Kaprielian

发明人： Steven A. Kunsman ,  Ismail I. Jouny ,  Stephen Kaprielian

IPC分类号： G06F19/00 ,  H02H3/42 ,  G01R31/08

CPC分类号： H02H1/0015 ,  G01R31/025 ,  H02H1/0092 ,  H02H3/05

摘要： An apparatus, system, and method for detecting high impedance faults in electrical power lines using a composite high impedance fault detection system having a voter logic that samples the logical outputs from a plurality of independent high impedance detection systems and determines a high impedance fault if any two of the plurality of independent high impedance detection systems indicates a high impedance fault. Preferably, the plurality of high impedance detection systems include a wavelet based high impedance fault detection system having a first logical output, a higher order statistics based high impedance fault detection system having a second logical output, and a neural net based high impedance fault detection system having a third logical output. Preferably, each of the plurality of high impedance fault detection systems includes an independent high impedance fault detection application that independently detects a high impedance fault on the electrical power line.

摘要翻译： 一种用于使用复合高阻抗故障检测系统检测电力线中的高阻抗故障的装置，系统和方法，所述复合高阻抗故障检测系统具有从多个独立高阻抗检测系统对逻辑输出进行采样的选民逻辑，并且如果有的话，确定高阻抗故障 多个独立的高阻抗检测系统中的两个表示高阻抗故障。 优选地，多个高阻抗检测系统包括具有第一逻辑输出的基于小波的高阻抗故障检测系统，具有第二逻辑输出的基于高阶统计的高阻抗故障检测系统以及基于神经网络的高阻抗故障检测系统 具有第三逻辑输出。 优选地，多个高阻抗故障检测系统中的每一个包括独立地检测电力线路上的高阻抗故障的独立的高阻抗故障检测应用。

公开(公告)号：US20110307114A1

公开(公告)日：2011-12-15

申请号：US13173838

申请日：2011-06-30

申请人： Steven A. Kunsman ,  Jean-Charles Tournier ,  Thomas Werner

发明人： Steven A. Kunsman ,  Jean-Charles Tournier ,  Thomas Werner

IPC分类号： G06F1/28 ,  G06F1/26

CPC分类号： H02J13/00 ,  G06F9/5077 ,  H02H7/261 ,  H02J13/001

摘要： Exemplary embodiments provide separate SA system-level functionalities or tasks, which are conventionally performed by a multitude of distinct station-level devices, through a single SA device having a plurality of Processing Units (PU). The latter are either distinct Central Processing Units (CPUs) mounted on the same processor board, or distinct processing cores of a single multi-core CPU sharing the same Random Access Memory (RAM). Virtualization techniques are used in supporting multiple instances of Operating Systems (OS) on the plurality of PUs, to create distinct and mutually isolated execution environments are created. Each of these execution environments hosts a single functionality out of a Supervisory Control And Data Acquisition (SCADA) functionality, a gateway functionality, an engineering workplace functionality, and a firewall functionality.

摘要翻译： 示例性实施例提供单独的SA系统级功能或任务，其通常由具有多个处理单元（PU）的单个SA设备通常由多个不同的站级设备执行。 后者是安装在同一处理器板上的不同的中央处理单元（CPU），或共享相同随机存取存储器（RAM）的单个多核CPU的不同处理核心。 虚拟化技术被用于支持多个PU上的操作系统（OS）的多个实例，以创建不同且相互隔离的执行环境。 这些执行环境中的每一个都从监控和数据采集（SCADA）功能，网关功能，工程工作场所功能和防火墙功能中承载单个功能。

公开(公告)号：US5963734A

公开(公告)日：1999-10-05

申请号：US825756

申请日：1997-04-03

申请人： William J. Ackerman ,  Steven A. Kunsman

发明人： William J. Ackerman ,  Steven A. Kunsman

IPC分类号： G06F9/44

CPC分类号： G05B23/0256 ,  G05B19/0428 ,  G05B2219/24036 ,  G05B2219/24215 ,  G06F9/4443 ,  Y02B70/3241 ,  Y04S20/227

摘要： Method and apparatus for performing point to point verification of devices in a SCADA system are provided. An intelligent electronic device (IED), having two modes of operation--normal and simulation--provides simulated IED data to a SCADA device on command. The IED is capable of continuing to perform its normal functions of monitoring a process under control during the simulation mode. The IED accepts simulation data either locally through a user interface or from a SCADA device over/through a communication port. The simulation data is then stored in a memory area of the IED. During simulation mode, the IED does not update the memory area but rather provides data from this area to a SCADA device on command.

摘要翻译： 提供了用于对SCADA系统中的设备进行点对点验证的方法和装置。 具有两种操作模式（智能电子设备）的智能电子设备（IED）可以通过命令向SCADA设备提供模拟的IED数据。 IED能够在模拟模式期间继续执行监视正在进行控制的过程的正常功能。 IED通过用户界面本地或通过通信端口从SCADA设备接收模拟数据。 然后将仿真数据存储在IED的存储器区域中。 在仿真模式下，IED不会更新内存区域，而是根据命令将该区域的数据提供给SCADA设备。