Phase locked loop frequency synthesizer with translation reference loop

    公开(公告)号:US12021539B1

    公开(公告)日:2024-06-25

    申请号:US18126380

    申请日:2023-03-24

    发明人: Justin Crooks

    IPC分类号: H03L7/093 H03L7/099 H03L7/18

    CPC分类号: H03L7/093 H03L7/0991 H03L7/18

    摘要: A translation reference loop frequency synthesizer for generating an output signal with sub-Hz frequency steps over a full octave. The synthesizer has a phase lock loop circuit and a translation reference loop. The phase lock loop circuit generates a phase lock oscillator output signal based on a phase lock feedback signal and a phase lock reference signal. The translation reference loop generates the phase lock reference signal based on mixing a translation reference frequency signal and a translation reference loop divided signal. The translation reference loop includes a series of translation loop dividers for generating the translation reference loop divided signal by dividing a frequency of the phase lock oscillator output signal. The translation reference loop includes a translation reference frequency generator for generating the translation reference frequency signal.