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公开(公告)号：US20120037973A1
公开(公告)日：2012-02-16
申请号：US13281083
申请日：2011-10-25
Applicant: Kenji GOMIKAWA , Tadashi Iguchi , Mitsuhiro Noguchi , Shoichi Watanabe
Inventor： Kenji GOMIKAWA , Tadashi Iguchi , Mitsuhiro Noguchi , Shoichi Watanabe
IPC: H01L29/788 , H01L29/792
CPC classification number: H01L29/792 , H01L27/115 , H01L27/11521 , H01L27/11524
Abstract: A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.
Abstract translation: 存储单元包括浮置栅电极，第一电极间绝缘膜和控制栅电极。 外围晶体管包括下电极，第二电极间绝缘膜和上电极。 下电极和上电极通过设置在第二电极间绝缘膜上的开口电连接。 第一和第二电极间绝缘膜包括高电容率材料，第一电极间绝缘膜具有第一结构，第二电极间绝缘膜具有与第一结构不同的第二结构。
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公开(公告)号：US07804123B2
公开(公告)日：2010-09-28
申请号：US11958732
申请日：2007-12-18
Applicant: Shoichi Watanabe
Inventor： Shoichi Watanabe
IPC: H01L29/788
CPC classification number: H01L27/11524 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42336 , H01L29/66825 , H01L29/7881
Abstract: A nonvolatile semiconductor memory according to an example of the present invention includes first and second diffusion layers, a channel formed between the first and second diffusion layers, a gate insulating film formed on the channel, a floating gate electrode formed on the gate insulating film, an inter-gate insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-gate insulating film. An end portion of the inter-gate insulating film in a direction of channel length is on an inward side of a side surface of the floating gate electrode or a side surface of the control gate electrode.
Abstract translation: 根据本发明实施例的非易失性半导体存储器包括第一和第二扩散层，形成在第一和第二扩散层之间的沟道，形成在沟道上的栅极绝缘膜，形成在栅极绝缘膜上的浮置栅电极， 形成在浮置栅电极上的栅极间绝缘膜，以及形成在栅极间绝缘膜上的控制栅电极。 栅极间绝缘膜的沟道长度方向的端部位于浮置栅电极的侧面的内侧或控制栅电极的侧面。
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公开(公告)号：US5720341A
公开(公告)日：1998-02-24
申请号：US747509
申请日：1996-11-12
Applicant: Mikio Watanabe , Takayuki Yasutake , Shoichi Watanabe , Yuji Hasegawa
Inventor： Mikio Watanabe , Takayuki Yasutake , Shoichi Watanabe , Yuji Hasegawa
CPC classification number: F28F9/002 , F28D1/024 , F28D1/0333 , F28D1/0341 , F28D1/0435 , F28F3/027 , F28D2021/0084 , F28D2021/0094 , F28F2210/04 , F28F2215/02 , F28F2270/00
Abstract: A duplex heat exchanger of the so-called stacked type has in principle a plurality of plate-shaped tubular elements (1) which are stacked side by side or one on another and a plurality of fins (2) each intervening between the adjacent tubular elements. Each tubular element is composed of flat tubular segments (3a, 4a) separated from each other and each communicating with one of bulged header portions (3b, 4b) of the tubular element, so that flow paths (3, 4) for heat exchanging media are formed through each tubular element. Two or more unit heat exchangers (X, Y) are defined integral with each other within the duplex heat exchanger, since the adjacent tubular elements (1) communicate with each other through the header portions (3b, 4b).
Abstract translation: 所谓堆叠式的双相热交换器原则上具有多个彼此并排或彼此堆叠的板状管状元件（1），以及分别介于相邻的管状元件之间的多个翅片（2） 。 每个管状元件由彼此分离的平坦的管状部分（3a，4a）组成，并且每个与管状元件的凸起的头部（3b，4b）中的一个连通，从而使用于热交换介质的流动路径（3,4） 通过每个管状元件形成。 由于相邻的管状元件（1）通过集管部分（3b，4b）彼此连通，所以两个或多个单元热交换器（X，Y）在双工热交换器内彼此一体形成。
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4.发明授权Ribbon protector including electro-conductive elements and platen gap adjustment device incorporating the same 失效带状保护器包括导电元件和包括该导电元件的压板间隙调节装置
公开(公告)号：US4929102A
公开(公告)日：1990-05-29
申请号：US131093
申请日：1987-12-10
Applicant: Minoru Mizutani , Hiroshi Kikuchi , Shoichi Watanabe , Kuniharu Hayashi , Masanori Maekawa
Inventor： Minoru Mizutani , Hiroshi Kikuchi , Shoichi Watanabe , Kuniharu Hayashi , Masanori Maekawa
Abstract: A ribbon protector is used for protecting paper from contamination by an ink ribbon in a printer, where the protector is inserted between paper located between a platen and a printing head. The printing head facing the platen performs spacing movement for printing. Two connected plate-like elements are provided with through openings for passage of the pin of the printing head. Mutually engageable electroconductive elements are provided on the inner walls of the two plate-like elements, at least in the area where they are compressed by the tip of the printing head, and spacers which are made from resilient materials are located between the two plate-like elements.
Abstract translation: 带状保护器用于防止纸张被打印机中的墨带污染，其中保护器插入在位于压板和打印头之间的纸张之间。 面向压盘的打印头执行打印的间隔运动。 两个连接的板状元件设置有用于打印头的销通过的通孔。 至少在打印头的顶端被压缩的区域中，两个板状元件的内壁上设有相互接合的导电元件，并且由弹性材料制成的间隔件位于两个板状元件之间， 像元素。
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公开(公告)号：US09095047B2
公开(公告)日：2015-07-28
申请号：US13791349
申请日：2013-03-08
Applicant: Shoichi Watanabe
Inventor： Shoichi Watanabe
CPC classification number: H05K5/0017 , H05K7/20963
Abstract: In one implementation a display apparatus, a display area of a display screen of a display panel is defined by edge portions of a first window formed in a first frame body. The first frame body is formed from a thin synthetic resin sheet and has upper airflow passages and side airflow passages formed therein. An outer communication portion of each of the upper airflow passages and an outer communication portion of each of the side airflow passages are exposed inside holes formed in a second frame body disposed in front of the first frame body. An inner communication portion of the upper airflow passage and an inner communication portion of the side airflow passage are exposed inside the edge portions of a second window of the second frame body. A space formed between the display panel and a cover plate communicates with the outer space via the upper airflow passages and the side airflow passages.
Abstract translation: 在一个实施方式中，显示装置，显示面板的显示屏幕的显示区域由形成在第一框架体中的第一窗口的边缘部分限定。 第一框架体由薄的合成树脂板形成，并且具有形成在其中的上部气流通道和侧部气流通道。 每个上部气流通道的外部连通部分和每个侧部气流通道的外部连通部分暴露在形成在设置在第一框架体前方的第二框架体中的孔内。 上部气流通道的内部连通部分和侧部气流通道的内部连通部分暴露在第二框架体的第二窗口的边缘部分的内部。 形成在显示面板和盖板之间的空间经由上部气流通路和侧部气流通路与外部空间连通。
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Patent Agency Ranking
6.发明授权Method of controlling criticality of nuclear fuel cycle facility, method of producing uranium dioxide powder, reactor fuel rod, and fuel assembly 有权控制核燃料循环设备临界性的方法，生产二氧化铀粉的方法，反应堆燃料棒和燃料组件公开(公告)号：US08130896B2
公开(公告)日：2012-03-06
申请号：US12120518
申请日：2008-05-14
Applicant: Shoichi Watanabe , Ishi Mitsuhashi , Kenichi Yoshioka
Inventor： Shoichi Watanabe , Ishi Mitsuhashi , Kenichi Yoshioka
IPC: G21C3/00
Abstract: A method of controlling the criticality of a nuclear fuel cycle facility includes steps of producing a reactor fuel by adding less than 0.1% by weight of gadolinia to a uranium dioxide powder with a uranium enrichment of greater than 5% by weight and controlling the effective neutron multiplication factor of a uranium dioxide system in a step of handling the reactor fuel to be less than or equal to the maximum of the effective neutron multiplication factor of a uranium dioxide system with a uranium enrichment of 5% by weight.
Abstract translation: 控制核燃料循环设备的关键性的方法包括以下步骤：通过将钆浓度小于5重量％的铀二氧化物粉末加入少于0.1重量％的氧化钆来生产反应堆燃料，并控制有效中子 处理反应堆燃料的步骤中二氧化铀系统的倍增系数小于或等于铀浓缩浓度为5重量％的二氧化铀系统的有效中子倍增系数的最大值。
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公开(公告)号：US20080142870A1
公开(公告)日：2008-06-19
申请号：US11958732
申请日：2007-12-18
Applicant: Shoichi Watanabe
Inventor： Shoichi Watanabe
IPC: H01L29/788
CPC classification number: H01L27/11524 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42336 , H01L29/66825 , H01L29/7881
Abstract: A nonvolatile semiconductor memory according to an example of the present invention includes first and second diffusion layers, a channel formed between the first and second diffusion layers, a gate insulating film formed on the channel, a floating gate electrode formed on the gate insulating film, an inter-gate insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-gate insulating film. An end portion of the inter-gate insulating film in a direction of channel length is on an inward side of a side surface of the floating gate electrode or a side surface of the control gate electrode.
Abstract translation: 根据本发明实施例的非易失性半导体存储器包括第一和第二扩散层，形成在第一和第二扩散层之间的沟道，形成在沟道上的栅极绝缘膜，形成在栅极绝缘膜上的浮置栅电极， 形成在浮置栅电极上的栅极间绝缘膜，以及形成在栅极间绝缘膜上的控制栅电极。 栅极间绝缘膜的沟道长度方向的端部位于浮置栅电极的侧面的内侧或控制栅电极的侧面。
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公开(公告)号：US5560985A
公开(公告)日：1996-10-01
申请号：US127452
申请日：1993-09-27
Applicant: Shoichi Watanabe , Hirokazu Inoguchi , Yoshihiro Kanzaka , Yoshiharu Tanaka , Hideji Ikehara , Ryuji Saiki , Nobukatsu Yamato , Tomohiro Mori , Minoru Senna
Inventor： Shoichi Watanabe , Hirokazu Inoguchi , Yoshihiro Kanzaka , Yoshiharu Tanaka , Hideji Ikehara , Ryuji Saiki , Nobukatsu Yamato , Tomohiro Mori , Minoru Senna
CPC classification number: B29C70/081 , A43B23/086 , A43B23/16 , B32B5/28 , B29K2101/12 , B29K2105/0809 , B29K2105/0854 , B29K2105/128 , B29L2009/00 , Y10T428/1366 , Y10T442/339 , Y10T442/352 , Y10T442/3707 , Y10T442/494
Abstract: The present invention provides a molding sheet material having a sandwich structure produced by preparing a fiber reinforced thermoplastic resin layer (A) reinforced with a woven fabric or a knitted web and a fiber reinforced thermoplastic resin layer (B) reinforced with a random mat and using the layer (A) as a core layer and the layer (B) as a skin layer, or using the layer (B) as a core layer and the layer (A) as a skin layer. When this sheet material is molded into a three-dimensional structure, the layer (B) serves as a cushion to prevent the occurrence of a wrinkle or a crease in the layer (A). A toe puff for a safety shoe having a light weight and excellent pressing resistance can be prepared through the molding of this sheet material. In the sheet materials, the core layer or the skin layer consisting of a fiber reinforced thermoplastic resin reinforced with a woven fabric or a knitted web of a reinforcing fiber may be prepared from a woven fabric or a knitted web of a reinforcing fiber alone.
Abstract translation: 本发明提供一种具有夹层结构的成型片材，其通过制备由机织织物或编织幅材增强的纤维增强热塑性树脂层（A）和用随机垫强化的纤维增强热塑性树脂层（B）制备，并使用 作为芯层的层（A）和作为表层的层（B），或者使用层（B）作为芯层，并且层（A）作为表层。 当该片材被模制成三维结构时，层（B）用作衬垫以防止在层（A）中出现褶皱或褶皱。 通过该片材的成型，可以制备具有重量轻且耐冲击性优异的安全鞋的脚趾吹气。 在片状材料中，由机织物增强的纤维增强热塑性树脂或增强纤维的针织网构成的芯层或表皮层可以由单独的增强纤维的机织织物或针织网制备。
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公开(公告)号：US5256475A
公开(公告)日：1993-10-26
申请号：US967821
申请日：1992-10-28
Applicant: Ryota Koyanagi , Mikiya Fujii , Shoichi Watanabe , Hirokazu Inoguchi
Inventor： Ryota Koyanagi , Mikiya Fujii , Shoichi Watanabe , Hirokazu Inoguchi
CPC classification number: D03D15/00 , D10B2101/12 , D10B2331/061 , D10B2401/041 , D10B2505/02 , Y10S428/902 , Y10T442/3252
Abstract: A fabric for a fiber-reinforced thermoplastic composite material is disclosed, which comprises the warp and the weft wherein the warp comprises reinforcing fiber and the weft comprises high molecular weight grade polyether ether ketone resin yarns and low molecular weight grade polyether ether ketone resin yarns, or wherein the warp comprises reinforcing fiber and at least one of high molecular weight grade polyether ether ketone resin yarns and low molecular weight grade polyether ether ketone resin yarns and the weft comprises reinforcing fiber and at least one of high molecular weight grade polyether ether ketone resin yarns and low molecular weight grade polyethe ether ketone resin yarns. The fabric can be laminated or molded into a product having an excellent toughness and shock resistance in almost the same heating time as the conventional one.
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10.发明授权Method for deleting unused gates and method for manufacturing master-slice semiconductor integrated circuit device using the deleting method 失效删除未使用的门的方法和使用该删除方法制造母片半导体集成电路器件的方法
公开(公告)号：US4960724A
公开(公告)日：1990-10-02
申请号：US378143
申请日：1989-07-11
Applicant: Shoichi Watanabe , Takayuki Takei , Terumine Hayashi , Takashi Natabe
Inventor： Shoichi Watanabe , Takayuki Takei , Terumine Hayashi , Takashi Natabe
IPC: H01L27/04 , G06F17/50 , H01L21/82 , H01L21/822 , H01L27/118 , H03K19/173
CPC classification number: G06F17/505 , G06F17/5068
Abstract: A method is provided for manufacturing a master slice semiconductor integrated circuit device. Initially, a first total circuit diagram which is to be reformed into a master slice semiconductor integrated circuit device is defined. First and second circuit points on the first total circuit block which are to be used respectively as input and output terminals of the master slice semiconductor integrated circuit device are specified. Next, signal transmitting paths are successively traced from the output to the input of each logic gate located in the signal transmitting paths in actual use. In the course of the tracing, these traced gates are marked and the logic gates actually in use are identified. As a result, in addition to those logic gates having unused output terminals, the gates constituting a closed loop isolated from the signal transmitting paths for transmitting substantial output signals are identified as unnecessary gates and deleted. Further, gates outputting only a fixed value are determined and designated unnecessary gates which are also deleted.
Abstract translation: 提供一种用于制造母片半导体集成电路器件的方法。 首先，定义要重整成主分片半导体集成电路器件的第一总电路图。 指定要分别用作主分片半导体集成电路器件的输入和输出端的第一总电路块上的第一和第二电路点。 接下来，在实际使用中，信号发送路径从位于信号发送路径中的每个逻辑门的输出连续追踪。 在跟踪过程中，这些跟踪的门被标记，并且确定了实际使用的逻辑门。 结果，除了具有未使用的输出端的逻辑门之外，构成与用于发送实质输出信号的信号发送路径隔离的闭环的门被识别为不必要的门并被删除。 此外，确定仅输出固定值的门，并指定也被删除的不必要门。
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