公开(公告)号：US20120327305A1

公开(公告)日：2012-12-27

申请号：US13604855

申请日：2012-09-06

申请人： Tomokuni YAMAGUCHI ,  Norihiko Mizobata ,  Shirou Yoshioka

发明人： Tomokuni YAMAGUCHI ,  Norihiko Mizobata ,  Shirou Yoshioka

IPC分类号： H04N5/222

CPC分类号： H04N5/44 ,  H04N5/63 ,  H04N21/4436

摘要： In a video audio processing device, a signal processing block (11, 12) includes an instruction memory (111, 121) and performs signal processing in accordance with a program loaded into the instruction memory. A main storage section (20) has a self-refresh function and is accessible from the signal processing block. An auxiliary storage section (30) stores the program for making the signal processing block perform the signal processing. Upon receipt of a standby instruction, a control section (15) performs control in such a manner as to transfer the program from the auxiliary storage section to the main storage section, and set self-refresh in the main storage section, and upon receipt of a return instruction, performs control in such a manner as to cancel the self-refresh in the main storage section, load the program from the main storage section to the instruction memory in the signal processing block, and activate the signal processing block.

摘要翻译： 在视频音频处理装置中，信号处理块（11,12）包括指令存储器（111,121），并根据加载到指令存储器中的程序进行信号处理。 主存储部分（20）具有自刷新功能，并且可从信号处理块访问。 辅助存储部分（30）存储用于使信号处理块执行信号处理的程序。 控制部（15）在接收到备用指示时，以从辅助存储部向主存储部传送程序的方式进行控制，在主存储部中设置自刷新，并且在接收到 返回指令以取消主存储部中的自刷新的方式进行控制，将程序从主存储部加载到信号处理块中的指令存储器，并且激活信号处理块。

公开(公告)号：US07904675B2

公开(公告)日：2011-03-08

申请号：US12498623

申请日：2009-07-07

申请人： Shirou Yoshioka

发明人： Shirou Yoshioka

IPC分类号： G06F12/00

CPC分类号： G06F12/127 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0864

摘要： A cache memory has a set associative scheme and includes a plurality of ways made up of entries, each entry holding data and a tag; a first holding unit holds, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit, included in a first way among the ways, holds, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit replaces control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein the control unit is further operable to store data into the entry of the way other than the first way.

摘要翻译： 高速缓存存储器具有集合关联方案，并且包括由条目组成的多个方式，每个条目保持数据和标签; 第一保持单元以各种方式保存指示以该方式优先存储的数据类型的优先级属性; 以第一方式包含的第二保持单元，对于第一方式的每个条目，保持指示保存在该条目中的数据类型的数据属性; 并且控制单元通过对由第一保持单元保持的优先级属性与从处理器输出的数据属性相匹配的方式进行优先排序来替换对条目的控制，其中，所述控制单元还可操作以将数据存储到除 第一路。

公开(公告)号：US07774281B2

公开(公告)日：2010-08-10

申请号：US11152085

申请日：2005-06-15

申请人： Minoru Okamoto ,  Katsuhiko Ueda ,  Shirou Yoshioka ,  Tetsuji Kishi

发明人： Minoru Okamoto ,  Katsuhiko Ueda ,  Shirou Yoshioka ,  Tetsuji Kishi

IPC分类号： G06F21/00

CPC分类号： G06F21/10

摘要： A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits a license request for using a function standard required for realizing the function to a license management device. The license management device receives the usage license request and correspondingly transmits an authorization for using the function standard to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device only when the usage authorization is received. The contents distribution device transmits the information contents to the terminal device only when the usage authorization is received.

摘要翻译： 终端装置向内容发布装置发送其设备信息和获取信息内容的请求。 内容分发装置根据获取请求中指定的信息内容和设备信息生成分发用于实现终端装置中的信息内容的程序的请求，并发送使用实现功能所需的功能标准的许可请求 到许可证管理设备。 许可证管理装置接收使用许可证请求，并相应地向程序发布装置和内容分发装置发送使用功能标准的授权。 程序分发装置仅在接收到使用授权时将程序发送到终端装置。 内容分发装置仅在接收到使用授权时才将该信息内容发送到终端装置。

公开(公告)号：US07574572B2

公开(公告)日：2009-08-11

申请号：US11898601

申请日：2007-09-13

申请人： Shirou Yoshioka

发明人： Shirou Yoshioka

IPC分类号： G06F12/00

CPC分类号： G06F12/127 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0864

摘要： A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among the ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from the processor, (ii) all of the following attributes match: the data attribute of the entry; the data attribute outputted from the processor; and the priority attribute of the first way, and (iii) an entry of a way other than the first way does not hold valid data, the entry being one of the entries that belong to the selected set, the control unit is further operable to store data into the entry of the way other than the first way.

摘要翻译： 根据本发明的高速缓冲存储器是具有集合关联方案的高速缓冲存储器，包括：多个方式，每个方式由条目组成，每个条目保存数据和标签; 第一保持单元，用于以每一方式保存指示以该方式优先存储的数据类型的优先级属性; 第二保持单元，其至少以所述方式中的第一方式被包括，并且可操作地对于所述第一方式的每个条目保存指示保存在所述条目中的数据类型的数据属性; 以及控制单元，其可操作以通过对由所述第一保持单元保持的优先级属性与从处理器输出的数据属性相匹配的方式来对所述条目执行替换控制，其中当发生高速缓存未命中时，以及（i）有效数据 在属于基于从处理器输出的地址选择的集合的条目之中的第一路径的条目中保存;（ii）所有以下属性都匹配：条目的数据属性; 从处理器输出的数据属性; 和所述第一方式的优先级属性，以及（iii）除了所述第一方式之外的方式的条目不保存有效数据，所述条目是属于所选集合的条目之一，所述控制单元还可操作为 将数据存储到不同于第一种方式的条目中。

公开(公告)号：US20050268041A1

公开(公告)日：2005-12-01

申请号：US11137560

申请日：2005-05-26

申请人： Shirou Yoshioka

发明人： Shirou Yoshioka

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F12/12

CPC分类号： G06F12/127 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0864

摘要： A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among the ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from the processor, (ii) all of the following attributes match: the data attribute of the entry; the data attribute outputted from the processor; and the priority attribute of the first way, and (iii) an entry of a way other than the first way does not hold valid data, the entry being one of the entries that belong to the selected set, the control unit is further operable to store data into the entry of the way other than the first way.

摘要翻译： 根据本发明的高速缓冲存储器是具有集合关联方案的高速缓冲存储器，包括：多个方式，每个方式由条目组成，每个条目保存数据和标签; 第一保持单元，用于以每一方式保存指示以该方式优先存储的数据类型的优先级属性; 第二保持单元，其至少以所述方式中的第一方式被包括，并且可操作地对于所述第一方式的每个条目保存指示保存在所述条目中的数据类型的数据属性; 以及控制单元，其可操作以通过对由所述第一保持单元保持的优先级属性与从处理器输出的数据属性相匹配的方式来对所述条目执行替换控制，其中，当发生高速缓存未命中时，以及（i）有效数据 在属于基于从处理器输出的地址选择的集合的条目之中的第一路径的条目中保存;（ii）所有以下属性都匹配：条目的数据属性; 从处理器输出的数据属性; 和所述第一方式的优先级属性，以及（iii）除了所述第一方式之外的方式的条目不保存有效数据，所述条目是属于所选集合的条目之一，所述控制单元还可操作为 将数据存储到不同于第一种方式的条目中。

公开(公告)号：US08284323B2

公开(公告)日：2012-10-09

申请号：US12440713

申请日：2008-07-08

申请人： Tomokuni Yamaguchi ,  Norihiko Mizobata ,  Shirou Yoshioka

发明人： Tomokuni Yamaguchi ,  Norihiko Mizobata ,  Shirou Yoshioka

IPC分类号： H04N7/01

CPC分类号： H04N5/44 ,  H04N5/63 ,  H04N21/4436

摘要： In a video audio processing device, a signal processing block (11, 12) includes an instruction memory (111, 121) and performs signal processing in accordance with a program loaded into the instruction memory. A main storage section (20) has a self-refresh function and is accessible from the signal processing block. An auxiliary storage section (30) stores the program for making the signal processing block perform the signal processing. Upon receipt of a standby instruction, a control section (15) performs control in such a manner as to transfer the program from the auxiliary storage section to the main storage section, and set self-refresh in the main storage section, and upon receipt of a return instruction, performs control in such a manner as to cancel the self-refresh in the main storage section, load the program from the main storage section to the instruction memory in the signal processing block, and activate the signal processing block.

摘要翻译： 在视频音频处理装置中，信号处理块（11,12）包括指令存储器（111,121），并根据加载到指令存储器中的程序进行信号处理。 主存储部分（20）具有自刷新功能，并且可从信号处理块访问。 辅助存储部分（30）存储用于使信号处理块执行信号处理的程序。 控制部（15）在接收到备用指示时，以从辅助存储部向主存储部传送程序的方式进行控制，在主存储部中设置自刷新，并且在接收到 返回指令以取消主存储部中的自刷新的方式进行控制，将程序从主存储部加载到信号处理块中的指令存储器，并且激活信号处理块。

公开(公告)号：US20100073573A1

公开(公告)日：2010-03-25

申请号：US12440713

申请日：2008-07-08

申请人： Tomokuni Yamaguchi ,  Norihiko Mizobata ,  Shirou Yoshioka

发明人： Tomokuni Yamaguchi ,  Norihiko Mizobata ,  Shirou Yoshioka

IPC分类号： H04N9/64 ,  H04N5/44

CPC分类号： H04N5/44 ,  H04N5/63 ,  H04N21/4436

摘要： In a video audio processing device, a signal processing block (11, 12) includes an instruction memory (111, 121) and performs signal processing in accordance with a program loaded into the instruction memory. A main storage section (20) has a self-refresh function and is accessible from the signal processing block. An auxiliary storage section (30) stores the program for making the signal processing block perform the signal processing. Upon receipt of a standby instruction, a control section (15) performs control in such a manner as to transfer the program from the auxiliary storage section to the main storage section, and set self-refresh in the main storage section, and upon receipt of a return instruction, performs control in such a manner as to cancel the self-refresh in the main storage section, load the program from the main storage section to the instruction memory in the signal processing block, and activate the signal processing block.

摘要翻译： 在视频音频处理装置中，信号处理块（11,12）包括指令存储器（111,121），并根据加载到指令存储器中的程序进行信号处理。 主存储部分（20）具有自刷新功能，并且可从信号处理块访问。 辅助存储部分（30）存储用于使信号处理块执行信号处理的程序。 控制部（15）在接收到备用指示时，以从辅助存储部向主存储部传送程序的方式进行控制，在主存储部中设置自刷新，并且在接收到 返回指令以取消主存储部中的自刷新的方式进行控制，将程序从主存储部加载到信号处理块中的指令存储器，并且激活信号处理块。

公开(公告)号：US20080016299A1

公开(公告)日：2008-01-17

申请号：US11898601

申请日：2007-09-13

申请人： Shirou Yoshioka

发明人： Shirou Yoshioka

IPC分类号： G06F12/08

CPC分类号： G06F12/127 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0864

摘要： A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among the ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from the processor, (ii) all of the following attributes match: the data attribute of the entry; the data attribute outputted from the processor; and the priority attribute of the first way, and (iii) an entry of a way other than the first way does not hold valid data, the entry being one of the entries that belong to the selected set, the control unit is further operable to store data into the entry of the way other than the first way.

摘要翻译： 根据本发明的高速缓冲存储器是具有集合关联方案的高速缓冲存储器，包括：多个方式，每个方式由条目组成，每个条目保存数据和标签; 第一保持单元，用于以每一方式保存指示以该方式优先存储的数据类型的优先级属性; 第二保持单元，其至少以所述方式中的第一方式被包括，并且可操作地对于所述第一方式的每个条目保存指示保存在所述条目中的数据类型的数据属性; 以及控制单元，其可操作以通过对由所述第一保持单元保持的优先级属性与从处理器输出的数据属性相匹配的方式来对所述条目执行替换控制，其中当发生高速缓存未命中时，以及（i）有效数据 在属于基于从处理器输出的地址选择的集合的条目之中的第一路径的条目中保存;（ii）所有以下属性都匹配：条目的数据属性; 从处理器输出的数据属性; 和所述第一方式的优先级属性，以及（iii）除了所述第一方式之外的方式的条目不保存有效数据，所述条目是属于所选集合的条目之一，所述控制单元还可操作为 将数据存储到不同于第一种方式的条目中。

公开(公告)号：US07103738B2

公开(公告)日：2006-09-05

申请号：US10647260

申请日：2003-08-26

申请人： Takashi Yoneda ,  Tsutomu Kamiyoshi ,  Hiroshi Benno ,  Shirou Yoshioka ,  Tsuneo Uenishi

发明人： Takashi Yoneda ,  Tsutomu Kamiyoshi ,  Hiroshi Benno ,  Shirou Yoshioka ,  Tsuneo Uenishi

IPC分类号： G06F12/16 ,  G06F12/11

CPC分类号： G06F13/28

摘要： A backup memory, a DMA (direct memory access) controller, and a WDT (watch dog timer) are provided in addition to a CPU (central processing unit), a RAM (random access memory), and a peripheral circuit. The DMA controller exercises control so that respective data of the CPU, RAM and peripheral circuit is saved in the backup memory each time the CPU, being under normal operation, supplies a counter reset signal to the WDT, and so that the data that has been saved in the backup memory is restored to the CPU, the RAM and the peripheral circuit, respectively, if the WDT has detected a program runaway and outputted a time-over signal. Therefore, even in a case where a program runaway has occurred in the CPU, normal operation is permitted to be resumed from midway in the program.

摘要翻译： 除了CPU（中央处理单元），RAM（随机存取存储器）和外围电路之外，还提供备用存储器，DMA（直接存储器访问）控制器和WDT（看门狗定时器）。 DMA控制器进行控制，以使CPU，RAM和外围电路的每个数据都保存在备用存储器中，每当处于正常操作状态的CPU向WDT提供计数器复位信号时， 如果WDT检测到程序失控并输出超时信号，则保存在备份存储器中的数据被分别还原到CPU，RAM和外围电路。 因此，即使在CPU中发生程序失控的情况下，也可以在程序的中途恢复正常的动作。

公开(公告)号：US20060021025A1

公开(公告)日：2006-01-26

申请号：US11152085

申请日：2005-06-15

申请人： Minoru Okamoto ,  Katsuhiko Ueda ,  Shirou Yoshioka ,  Tetsuji Kishi

发明人： Minoru Okamoto ,  Katsuhiko Ueda ,  Shirou Yoshioka ,  Tetsuji Kishi

IPC分类号： G06F12/14

CPC分类号： G06F21/10

摘要： A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits a license request for using a function standard required for realizing the function to a license management device. The license management device receives the usage license request and correspondingly transmits an authorization for using the function standard to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device only when the usage authorization is received. The contents distribution device transmits the information contents to the terminal device only when the usage authorization is received.

摘要翻译： 终端装置向内容发布装置发送其设备信息和获取信息内容的请求。 内容分发装置根据获取请求中指定的信息内容和设备信息生成分发用于实现终端装置中的信息内容的程序的请求，并发送使用实现功能所需的功能标准的许可请求 到许可证管理设备。 许可证管理装置接收使用许可证请求，并相应地向程序发布装置和内容分发装置发送使用功能标准的授权。 程序分发装置仅在接收到使用授权时将程序发送到终端装置。 内容分发装置仅在接收到使用授权时才将该信息内容发送到终端装置。