Transmitter architectures for communications systems
    1.
    发明授权
    Transmitter architectures for communications systems 有权
    用于通信系统的发射机架构

    公开(公告)号:US06721368B1

    公开(公告)日:2004-04-13

    申请号:US09519734

    申请日:2000-03-04

    IPC分类号: H04L2704

    摘要: Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or the entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.

    摘要翻译: 具有比传统发射机架构具有改进性能的通信系统的发射机架构。 这些改进包括以下组合:控制信号的响应时间更快,线性度更好,干扰减少,功耗降低,电路复杂度降低,成本降低。 对于蜂窝应用,这些改进可以导致系统容量增加,电话尺寸更小,通话和待机时间增加,以及对产品的更多接受。 提供电路以加快控制信号的响应时间。 发送信号路径中的各种元件的控制回路被集成。 增益控制机制允许精确调整输出发射功率电平。 提供控制机制以在不需要时将功率放大器或整个发射信号路径断电。 控制发射信号路径中的各种元件的增益以减少输出发射功率的瞬变,并且还确保瞬变是向下的。

    Digital-to-analog interface circuit having adjustable time response
    2.
    发明授权
    Digital-to-analog interface circuit having adjustable time response 有权
    具有可调时间响应的数模转换接口电路

    公开(公告)号:US06292122B1

    公开(公告)日:2001-09-18

    申请号:US09517766

    申请日:2000-03-04

    IPC分类号: H03M300

    摘要: An interface circuit for converting a digital signal to an analog signal. The interface circuit includes a time response adjustment circuit, a modulator, and a filter. The time response adjustment circuit receives the digital signal and generates an adjusted signal. The modulator couples to the time response adjustment circuit, receives the adjusted signal, and generates a modulator signal. The filter couples to the modulator, receives the modulator signal, and generates the analog signal. The analog signal has a time response that is modified by the time response adjustment circuit. In an embodiment, the time response adjustment circuit includes a gain element, a delay element, and a summer. The gain element receives and scales the digital signal by a scaling factor. The delay element receives and delays the digital signal by a time delay. The summer couples to the gain element and the delay element, sums the scaled signal from the gain element and the delayed signal from the delay element to generate the adjusted signal.

    摘要翻译: 一种用于将数字信号转换为模拟信号的接口电路。 接口电路包括时间响应调整电路,调制器和滤波器。 时间响应调整电路接收数字信号并产生调整信号。 调制器耦合到时间响应调整电路,接收经调整的信号,并产生调制器信号。 滤波器耦合到调制器,接收调制器信号,并产生模拟信号。 模拟信号具有由时间响应调整电路修改的时间响应。 在一个实施例中,时间响应调整电路包括增益元件,延迟元件和加法器。 增益元件以缩放因子接收和缩放数字信号。 延迟元件接收并延迟数字信号延时。 加法器与增益元件和延迟元件耦合,将来自增益元件的定标信号和来自延迟元件的延迟信号相加,以产生调整后的信号。

    Time acquisition in a wireless position determination system
    5.
    发明申请
    Time acquisition in a wireless position determination system 有权
    无线位置确定系统中的时间采集

    公开(公告)号:US20050003833A1

    公开(公告)日:2005-01-06

    申请号:US10840900

    申请日:2004-05-07

    申请人: Saed Younis

    发明人: Saed Younis

    CPC分类号: G01S19/05 G01S19/256

    摘要: A system and method for providing timing information to a wireless device in a position determination system is disclosed. A wireless device includes a reference signal receiver, a signal processor, a wireless communications transceiver and a GPS receiver. The wireless device is adapted to receive a reference signal, extract a snippet of the received reference signal, determine a time of reception for the snippet and transmit the snippet and time of reception to a position determination entity as part of a request for GPS aiding information. The position determination entity includes a timing source, a GPS memory for storing GPS satellite information, a reference signal memory, a communications interface, a signal processor and a control processor. The position determination entity is adapted to continually receive and store a reference signal along with an associated time of reception, and receive the snippet and timestamp transmitted from the wireless device. The position determination entity is further adapted to match the signal snippet to a portion of the stored reference signal, determine a time offset between the timestamp and the time of reception of the matched portion of the stored reference signal, prepare aiding information for the wireless device, synchronize the aiding information to the wireless device using the time offset, and transmit the synchronized aiding information to the wireless device. The wireless device is further adapted to receive the aiding information, including timing information to assist the wireless device in acquiring the GPS signals.

    摘要翻译: 公开了一种用于在位置确定系统中向无线设备提供定时信息的系统和方法。 无线设备包括参考信号接收器,信号处理器,无线通信收发器和GPS接收器。 无线设备适于接收参考信号,提取接收到的参考信号的片段,确定片段的接收时间,并将该片段和接收时间作为GPS辅助信息请求的一部分发送给位置确定实体 。 位置确定实体包括定时源,用于存储GPS卫星信息的GPS存储器,参考信号存储器,通信接口,信号处理器和控制处理器。 位置确定实体适于连续地接收和存储参考信号连同相关联的接收时间,并且接收从无线设备发送的片段和时间戳。 位置确定实体还适于将信号片段与存储的参考信号的一部分相匹配,确定所存储的参考信号的匹配部分的时间戳和接收时间之间的时间偏移,为无线装置准备辅助信息 使用时间偏移将辅助信息同步到无线设备,并将同步的辅助信息发送到无线设备。 无线设备还适于接收辅助信息,包括定时信息以帮助无线设备获取GPS信号。

    Time acquisition in a wireless position determination system
    6.
    发明授权
    Time acquisition in a wireless position determination system 有权
    无线位置确定系统中的时间采集

    公开(公告)号:US07302225B2

    公开(公告)日:2007-11-27

    申请号:US10840900

    申请日:2004-05-07

    申请人: Saed Younis

    发明人: Saed Younis

    IPC分类号: H04B7/185

    CPC分类号: G01S19/05 G01S19/256

    摘要: A system and method for providing timing information to a wireless device in a position determination system is disclosed. A wireless device includes a reference signal receiver, a signal processor, a wireless communications transceiver and a GPS receiver. The wireless device is adapted to receive a reference signal, extract a snippet of the received reference signal, determine a time of reception for the snippet and transmit the snippet and time of reception to a position determination entity as part of a request for GPS aiding information. The position determination entity includes a timing source, a GPS memory for storing GPS satellite information, a reference signal memory, a communications interface, a signal processor and a control processor. The position determination entity is adapted to continually receive and store a reference signal along with an associated time of reception, and receive the snippet and timestamp transmitted from the wireless device. The position determination entity is further adapted to match the signal snippet to a portion of the stored reference signal, determine a time offset between the timestamp and the time of reception of the matched portion of the stored reference signal, prepare aiding information for the wireless device, synchronize the aiding information to the wireless device using the time offset, and transmit the synchronized aiding information to the wireless device. The wireless device is further adapted to receive the aiding information, including timing information to assist the wireless device in acquiring the GPS signals.

    摘要翻译: 公开了一种用于在位置确定系统中向无线设备提供定时信息的系统和方法。 无线设备包括参考信号接收器,信号处理器,无线通信收发器和GPS接收器。 无线设备适于接收参考信号,提取接收到的参考信号的片段,确定片段的接收时间,并将该片段和接收时间作为GPS辅助信息请求的一部分发送给位置确定实体 。 位置确定实体包括定时源,用于存储GPS卫星信息的GPS存储器,参考信号存储器,通信接口,信号处理器和控制处理器。 位置确定实体适于连续地接收和存储参考信号连同相关联的接收时间,并且接收从无线设备发送的片段和时间戳。 位置确定实体还适于将信号片段与存储的参考信号的一部分相匹配,确定所存储的参考信号的匹配部分的时间戳和接收时间之间的时间偏移,为无线装置准备辅助信息 使用时间偏移将辅助信息同步到无线设备,并将同步的辅助信息发送到无线设备。 无线设备还适于接收辅助信息,包括定时信息以帮助无线设备获取GPS信号。

    Time acquisition in a wireless position determination system
    8.
    发明授权
    Time acquisition in a wireless position determination system 有权
    无线位置确定系统中的时间采集

    公开(公告)号:US06907224B2

    公开(公告)日:2005-06-14

    申请号:US10099096

    申请日:2002-03-15

    申请人: Saed Younis

    发明人: Saed Younis

    CPC分类号: G01S19/05 G01S19/256

    摘要: A system and method provide aiding information to a wireless device. The wireless device extracts a snippet of a received reference signal, generates a timestamp representing the time of reception thereof, and transmits the snippet and timestamp to a position determination entity (PDE). The PDE receives and stores a reference signal along with its reception time, and receive the snippet and timestamp from the wireless device. The PDE matches the snippet to a portion of the stored reference signal, and determines a time offset between the timestamp and the time of reception of the matched portion of the stored reference signal, The PDE then prepares the aiding information, synchronizes it to the wireless device using the time offset, and transmits the synchronized aiding information to the wireless device.

    摘要翻译: 系统和方法向无线设备提供辅助信息。 无线设备提取接收到的参考信号的片段,生成表示其接收时间的时间戳,并将该片段和时间戳发送到位置确定实体(PDE)。 PDE接收并存储参考信号及其接收时间,并从无线设备接收片段和时间戳。 PDE将片段与存储的参考信号的一部分相匹配,并且确定所存储的参考信号的匹配部分的时间戳和接收时间之间的时间偏移。然后,PDE准备辅助信息,将其与无线 设备使用时间偏移,并将同步的辅助信息发送到无线设备。

    Charge recovery logic including split level logic
    9.
    发明授权
    Charge recovery logic including split level logic 失效
    充电恢复逻辑包括分级逻辑

    公开(公告)号:US5378940A

    公开(公告)日:1995-01-03

    申请号:US102477

    申请日:1993-08-03

    IPC分类号: H03K19/00 H03K19/096

    CPC分类号: H03K19/0019 H03K19/0963

    摘要: In a pipelined logic circuit, switches are only enabled when voltage differentials across the switches are zero. The switches are configured during a restored state of voltage rails, and a swing in voltage on the rails results in a swing in output voltage to a set level. To restore the logic circuit with minimal energy dissipation and permit useful pipelining, the inputs are regenerated through an inverse logic circuit. The voltage rail then swings back to its restored level. Full forward and reverse pipelines are formed with the individual forward and inverse logic circuits with the pipelines being driven by multiphase clock rails. Each logic stage includes a logic gate and a pass gate.

    摘要翻译: 在流水线逻辑电路中,开关仅在开关上的电压差为零时才能使能。 在恢复电压轨状态期间配置开关,并且导轨上的电压摆幅导致输出电压的摆幅达到设定电平。 为了以最小的能量消耗来恢复逻辑电路并允许有用的流水线,输入通过反逻辑电路再生。 电压轨然后摆回到恢复的电平。 完整的正向和反向管道与单独的正向和反向逻辑电路形成,管道由多相时钟轨道驱动。 每个逻辑级包括逻辑门和通路。