公开(公告)号：US09094634B2

公开(公告)日：2015-07-28

申请号：US13910392

申请日：2013-06-05

Applicant: Yu Su ,  Mustafa H. Koroglu ,  Ruifeng Sun ,  Krishna Pentakota ,  Pio Balmelli ,  Ramin Khoini-Poorfard

Inventor： Yu Su ,  Mustafa H. Koroglu ,  Ruifeng Sun ,  Krishna Pentakota ,  Pio Balmelli ,  Ramin Khoini-Poorfard

IPC: H03F3/191 ,  H04N5/44 ,  H03F3/193 ,  H03F3/195 ,  H03F1/56 ,  H04N5/455

CPC classification number: H04N5/44 ,  H03F1/565 ,  H03F3/191 ,  H03F3/193 ,  H03F3/195 ,  H04N5/455

Abstract: An amplifier includes a negative gain amplifier, a load element, and a transconductance device. The negative gain amplifier has an input and an output. The load element has a first terminal coupled to a power supply voltage terminal, and a second terminal. The transconductance device has a first current electrode coupled to the second terminal of the load element, a control electrode coupled to the output of the negative gain amplifier, and a second current electrode coupled to the input of the negative gain amplifier.

Abstract translation: 放大器包括负增益放大器，负载元件和跨导器件。 负增益放大器具有输入和输出。 负载元件具有耦合到电源电压端子的第一端子和第二端子。 跨导器件具有耦合到负载元件的第二端子的第一电流电极，耦合到负增益放大器的输出的控制电极和耦合到负增益放大器的输入的第二电流电极。

公开(公告)号：US08428534B1

公开(公告)日：2013-04-23

申请号：US13250340

申请日：2011-09-30

Applicant: Ravi K. Kummaraguntla ,  Ruifeng Sun

Inventor： Ravi K. Kummaraguntla ,  Ruifeng Sun

IPC: H04B7/00 ,  H03K5/22

CPC classification number: H03G3/30

Abstract: Techniques are disclosed relating to radio frequency (RF) power detection. In one embodiment, a power detection unit is disclosed that includes a multiplier circuit configured to receive a first voltage of a voltage differential signal at gates of a first transistor pair and a second voltage of the voltage differential signal at gates of a second transistor pair. The first multiplier is configured to output a current that varies proportionally to a square of a voltage difference between the first and second voltages. In some embodiments, sources of the first transistor pair are coupled to sources of the second transistor pair, and the sources of the second transistor pair are coupled together. In some embodiments, the power detection unit is configured to compensate for mismatched transistors by applying offset voltages to bodies of transistors in the first and second transistor pairs.

Abstract translation: 公开了与射频（RF）功率检测有关的技术。 在一个实施例中，公开了一种功率检测单元，其包括乘法器电路，其被配置为在第二晶体管对的栅极处接收第一晶体管对的栅极处的电压差分信号的第一电压和电压差分信号的第二电压。 第一乘法器被配置为输出与第一和第二电压之间的电压差的平方成比例地变化的电流。 在一些实施例中，第一晶体管对的源极耦合到第二晶体管对的源极，并且第二晶体管对的源极耦合在一起。 在一些实施例中，功率检测单元被配置为通过向第一和第二晶体管对中的晶体管的主体施加偏移电压来补偿失配的晶体管。

公开(公告)号：US08339179B2

公开(公告)日：2012-12-25

申请号：US13584334

申请日：2012-08-13

Applicant: Ruifeng Sun ,  Yunteng Huang

Inventor： Ruifeng Sun ,  Yunteng Huang

IPC: G06G7/16

CPC classification number: G01R21/01 ,  H03G1/0088 ,  H03G3/3052

Abstract: In one form, a power converter for a power detector or the like includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node.

Abstract translation: 在一种形式中，用于功率检测器等的功率转换器包括第一导电类型的第一和第三晶体管，以及第二导电类型的第二和第四晶体管。 第一晶体管的控制电极接收第一偏置电压加上差分输入信号的正分量。 第二晶体管与第一晶体管串联耦合，并且具有接收第二偏置电压加上差分输入信号的负分量的控制电极。 第三晶体管使用第一偏置电压加上负分量进行偏置。 第四晶体管与第三晶体管串联耦合，并使用第二偏置电压加上正分量进行偏置。 第一和第三晶体管的公共互连点形成输出节点。

公开(公告)号：US08151029B2

公开(公告)日：2012-04-03

申请号：US12981769

申请日：2010-12-30

Applicant: Scott Haban ,  Dylan Hester ,  Ruifeng Sun

Inventor： Scott Haban ,  Dylan Hester ,  Ruifeng Sun

IPC: G06F13/00

CPC classification number: G06F13/4282

Abstract: A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.

Abstract translation: 解调器可以包括经由第一总线将解调器耦合到主机设备的第一数据和时钟焊盘，以及经由第二总线将解调器耦合到射频（RF）调谐器的第二数据和时钟焊盘。 该设备还可以包括用于将主机数据和主机时钟从第一总线耦合到第二总线的通过逻辑，并且在直通模式期间将调谐器数据从第二总线耦合到第一总线。 然而，在这种模式下，两条总线可能保持电气分离。 当禁用直通模式时，RF调谐器被屏蔽，避免了第一个总线上存在的噪声。

公开(公告)号：US20110102047A1

公开(公告)日：2011-05-05

申请号：US12611151

申请日：2009-11-03

Applicant: Ruifeng Sun ,  Yunteng Huang

Inventor： Ruifeng Sun ,  Yunteng Huang

IPC: H03L5/00 ,  G01R19/00

CPC classification number: G01R21/01 ,  H03G1/0088 ,  H03G3/3052

Abstract: In one form, a power detector includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node. In another form, a power detector compares an output of a power detector core to multiple threshold voltages in corresponding comparators.

Abstract translation: 在一种形式中，功率检测器包括第一导电类型的第一和第三晶体管，以及第二导电类型的第二和第四晶体管。 第一晶体管的控制电极接收第一偏置电压加上差分输入信号的正分量。 第二晶体管与第一晶体管串联耦合，并且具有接收第二偏置电压加上差分输入信号的负分量的控制电极。 第三晶体管使用第一偏置电压加上负分量进行偏置。 第四晶体管与第三晶体管串联耦合，并使用第二偏置电压加上正分量进行偏置。 第一和第三晶体管的公共互连点形成输出节点。 在另一种形式中，功率检测器将功率检测器核心的输出与相应比较器中的多个阈值电压进行比较。

公开(公告)号：US20110099310A1

公开(公告)日：2011-04-28

申请号：US12981769

申请日：2010-12-30

Applicant: Scott Haban ,  Dylan Hester ,  Ruifeng Sun

Inventor： Scott Haban ,  Dylan Hester ,  Ruifeng Sun

IPC: G06F13/36 ,  G06F13/00

CPC classification number: G06F13/4282

Abstract: A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.

Abstract translation: 解调器可以包括经由第一总线将解调器耦合到主机设备的第一数据和时钟焊盘，以及经由第二总线将解调器耦合到射频（RF）调谐器的第二数据和时钟焊盘。 该设备还可以包括用于将主机数据和主机时钟从第一总线耦合到第二总线的通过逻辑，并且在直通模式期间将调谐器数据从第二总线耦合到第一总线。 然而，在这种模式下，两条总线可能保持电气分离。 当禁用直通模式时，RF调谐器被屏蔽，避免了第一个总线上存在的噪声。

公开(公告)号：US08264255B2

公开(公告)日：2012-09-11

申请号：US12611151

申请日：2009-11-03

Applicant: Ruifeng Sun ,  Yunteng Huang

Inventor： Ruifeng Sun ,  Yunteng Huang

IPC: H03K5/153

CPC classification number: G01R21/01 ,  H03G1/0088 ,  H03G3/3052

Abstract: In one form, a power detector includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node. In another form, a power detector compares an output of a power detector core to multiple threshold voltages in corresponding comparators.

Abstract translation: 在一种形式中，功率检测器包括第一导电类型的第一和第三晶体管，以及第二导电类型的第二和第四晶体管。 第一晶体管的控制电极接收第一偏置电压加上差分输入信号的正分量。 第二晶体管与第一晶体管串联耦合，并且具有接收第二偏置电压加上差分输入信号的负分量的控制电极。 第三晶体管使用第一偏置电压加上负分量进行偏置。 第四晶体管与第三晶体管串联耦合，并使用第二偏置电压加上正分量进行偏置。 第一和第三晶体管的公共互连点形成输出节点。 在另一种形式中，功率检测器将功率检测器核心的输出与相应比较器中的多个阈值电压进行比较。

公开(公告)号：US20090292843A1

公开(公告)日：2009-11-26

申请号：US12154265

申请日：2008-05-21

Applicant: Scott Haban ,  Dylan Hester ,  Ruifeng Sun

Inventor： Scott Haban ,  Dylan Hester ,  Ruifeng Sun

IPC: G06F13/40 ,  G06F13/36

CPC classification number: G06F13/4282

Abstract: A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.

Abstract translation: 解调器可以包括经由第一总线将解调器耦合到主机设备的第一数据和时钟焊盘，以及经由第二总线将解调器耦合到射频（RF）调谐器的第二数据和时钟焊盘。 该设备还可以包括用于将主机数据和主机时钟从第一总线耦合到第二总线的通过逻辑，并且在直通模式期间将调谐器数据从第二总线耦合到第一总线。 然而，在这种模式下，两条总线可能保持电气分离。 当禁用直通模式时，RF调谐器被屏蔽，避免了存在于第一总线上的噪声。

公开(公告)号：US08385867B2

公开(公告)日：2013-02-26

申请号：US12493819

申请日：2009-06-29

Applicant: Aslamali A. Rafi ,  Chunyu Xin ,  Ruifeng Sun ,  Abhishek Kammula ,  Ramin Khoini-Poorfard ,  Alessandro Piovaccari ,  Peter J. Vancorenland

Inventor： Aslamali A. Rafi ,  Chunyu Xin ,  Ruifeng Sun ,  Abhishek Kammula ,  Ramin Khoini-Poorfard ,  Alessandro Piovaccari ,  Peter J. Vancorenland

IPC: H04B1/18

CPC classification number: H03J3/06 ,  H03J3/32 ,  H03J2200/10 ,  H03J2200/32 ,  H04N5/50

Abstract: In one embodiment, a set of tracking filters to be coupled between an amplifier and a mixer is provided. The tracking filters may be differently configured depending on band of operation. For example, a first set of the filters can be configured to maintain a substantially constant Q value across their operating bandwidth while a second set of the filters can be configured to maintain a substantially constant bandwidth across their operating bandwidth.

Abstract translation: 在一个实施例中，提供要耦合在放大器和混频器之间的一组跟踪滤波器。 根据操作频带，跟踪滤波器可以被不同地配置。 例如，可以将第一组滤波器配置为在其工作带宽上维持基本上恒定的Q值，而第二组滤波器可被配置为在其工作带宽上维持基本恒定的带宽。

公开(公告)号：US20120299623A1

公开(公告)日：2012-11-29

申请号：US13584334

申请日：2012-08-13

Applicant: Ruifeng Sun ,  Yunteng Huang

Inventor： Ruifeng Sun ,  Yunteng Huang

IPC: H03K5/22 ,  G06G7/12

CPC classification number: G01R21/01 ,  H03G1/0088 ,  H03G3/3052

Abstract: In one form, a power converter for a power detector or the like includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node.

Abstract translation: 在一种形式中，用于功率检测器等的功率转换器包括第一导电类型的第一和第三晶体管，以及第二导电类型的第二和第四晶体管。 第一晶体管的控制电极接收第一偏置电压加上差分输入信号的正分量。 第二晶体管与第一晶体管串联耦合，并且具有接收第二偏置电压加上差分输入信号的负分量的控制电极。 第三晶体管使用第一偏置电压加上负分量进行偏置。 第四晶体管与第三晶体管串联耦合，并使用第二偏置电压加上正分量进行偏置。 第一和第三晶体管的公共互连点形成输出节点。